xscale.v

一个视频信号输入的verilog源代码

// ================================================================================
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// 
// This reference design file, and your use thereof, is subject to and governed
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// warranties of merchantability, non-infringement, or fitness for a particular
// purpose, are specifically disclaimed.  By making this reference design file
// available, Altera expressly does not recommend, suggest or require that this
// reference design file be used in combination with any other product not
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// ================================================================================
//---------------------------------------------------------------------------
// X scaling
//---------------------------------------------------------------------------
`timescale 1ns/1ns

module xscale (
	       clk,
	       reset_n,

	       eof_in,

	       // input
	       rgb_in_en,
	       rgb_in,

	       // output
	       rgb_out_en,
	       rgb_out,
	       eol,
	       eof,

	       // control registers
	       xscale_reg,
	       xlen
	       );

  input clk;
  input reset_n;

  input eof_in;
  
  input rgb_in_en;
  input [17:0] rgb_in;

  output 	rgb_out_en;
  output [17:0] rgb_out;
  output 	eol;		// End of line
  output 	eof;		// End of frame

  input [15:0] 	xscale_reg;
  input [9:0] 	xlen;

  wire [21:0] 	next_pixel;
  wire [21:0] 	next_pixel2;

  reg pixel_en;

  reg [21:0] output_pixel;

  wire [3:0] 	scale_int = xscale_reg[15:12];
  wire [5:0] 	scale_frac = xscale_reg[11:6];

  //---------------------------------------------------------------------------
  //---------------------------------------------------------------------------
  reg [17:0] pixel1;
  reg [17:0] pixel2;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      pixel2 <= 18'b0;
    else if (rgb_in_en)
      pixel2 <= rgb_in;

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      pixel1 <= 18'b0;
    else if (rgb_in_en)
      pixel1 <= pixel2;

  reg [9:0] 	pixel_in;
  reg 		last_pixel;
  wire 		do_eol;
  wire 		do_pixel;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      pixel_in <= 10'b0;
    else if (do_eol)
      pixel_in <= 10'b0;
    else if (rgb_in_en)
      pixel_in <= pixel_in + 10'b1;

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      last_pixel <= 1'b0;
    else if (rgb_in_en & (pixel_in == xlen))
      last_pixel <= 1'b1;
    else if (do_eol)
      last_pixel <= 1'b0;

  assign 	do_pixel = (next_pixel <= {pixel_in, 12'b0});
  assign 	do_eol = last_pixel & ~do_pixel;
  
  reg 		eol;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      eol <= 1'b0;
    else eol <= do_eol;

  assign next_pixel = output_pixel + xscale_reg;
  assign next_pixel2 = next_pixel + xscale_reg;
  
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      output_pixel <= 22'h1000;
    else if (do_eol)
      output_pixel <= 22'h1000;
    else if (do_pixel)
      output_pixel <= next_pixel;

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      pixel_en <= 1'b0;
    else
      pixel_en <= do_pixel | do_eol;

  //---------------------------------------------------------------------------
  // Instantiate Multipliers
  //
  // One each for red, green and blue for each pixel buffer. May eventually be
  // reduced by resource sharing.
  //---------------------------------------------------------------------------
  wire [12:0] 	pixel1_red;
  wire [12:0] 	pixel1_green;
  wire [12:0] 	pixel1_blue;
  wire [11:0] 	pixel2_red;
  wire [11:0] 	pixel2_green;
  wire [11:0] 	pixel2_blue;

  reg [5:0] 	pixel2_fraction;
  // delay to avoid problem with output_pixel changing
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      pixel2_fraction <= 6'b0;
    else
      pixel2_fraction <= output_pixel[11:6];
  
  wire [6:0] 	pixel1_fraction = 7'b1000000 - {1'b0, pixel2_fraction};
  
  // pixel 1 red
  mult6x7 u_mult_1r (
		     .clock	(clk),
		     
		     .dataa	(pixel1[17:12]),
		     .datab	(pixel1_fraction),
		     
		     .result	(pixel1_red)
		     );

  // pixel 1 green
  mult6x7 u_mult_1g (
		     .clock	(clk),
		     
		     .dataa	(pixel1[11:6]),
		     .datab	(pixel1_fraction),
		     
		     .result	(pixel1_green)
		     );

  // pixel 1 blue
  mult6x7 u_mult_1b (
		     .clock	(clk),
		     
		     .dataa	(pixel1[5:0]),
		     .datab	(pixel1_fraction),
		     
		     .result	(pixel1_blue)
		     );

  // pixel 2 red
  mult6x6 u_mult_2r (
		     .clock	(clk),
		     
		     .dataa	(pixel2[17:12]),
		     .datab	(pixel2_fraction),
		     
		     .result	(pixel2_red)
		     );

  // pixel 2 green
  mult6x6 u_mult_2g (
		     .clock	(clk),
		     
		     .dataa	(pixel2[11:6]),
		     .datab	(pixel2_fraction),
		     
		     .result	(pixel2_green)
		     );

  // pixel 2 blue
  mult6x6 u_mult_2b (
		     .clock	(clk),
		     
		     .dataa	(pixel2[5:0]),
		     .datab	(pixel2_fraction),
		     
		     .result	(pixel2_blue)
		     );

  wire [5:0] red_out = (pixel1_red + pixel2_red) >> 6;
  wire [5:0] green_out = (pixel1_green + pixel2_green) >> 6;
  wire [5:0] blue_out = (pixel1_blue + pixel2_blue) >> 6;

  wire [17:0] rgb_out = {red_out, green_out, blue_out};

  wire rgb_out_en = pixel_en;

  reg  eof_r, eof_rr, eof_rrr, eof;
  // Correct eof for latency through x scaling
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
    begin
      eof_r <= 1'b0;
      eof_rr <= 1'b0;
      eof_rrr <= 1'b0;
      eof <= 1'b0;
    end
    else
    begin
      eof_r <= eof_in;
      eof_rr <= eof_r;
      eof_rrr <= eof_rr;
      eof <= eof_rrr;
    end
      
endmodule	// xscale