clip.v

一个视频信号输入的verilog源代码

// ================================================================================
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// ================================================================================
//---------------------------------------------------------------------------
// Input clipping
//---------------------------------------------------------------------------
`timescale 1ns/1ns

module clip (
	     clk,

	     // input samples and timing
	     clk_in_en,
	     y_in,
	     cb_in,
	     cr_in,
	     pixel,
	     line,

	     // output samples
	     clk_out_en,
	     y_out,
	     cb_out,
	     cr_out,

	     // clipping registers
	     xclips,
	     xclipe,
	     yclips,
	     yclipe
);

  input clk;		// 27 MHz

  // input samples and timing
  input clk_in_en;
  input [7:0] y_in;
  input [7:0] cb_in;
  input [7:0] cr_in;
  input [9:0] pixel;
  input [8:0] line;
  
  // output samples
  output       clk_out_en;
  output [7:0]  y_out;
  output [7:0]  cb_out;
  output [7:0]  cr_out;

  // clipping registers
  input [9:0]  xclips;
  input [9:0]  xclipe;
  input [8:0]  yclips;
  input [8:0]  yclipe;

  wire 	       clip_x = (pixel < xclips) | (pixel > xclipe);
  wire 	       clip_y = (line < yclips) | (line > yclipe);

  wire 	       clk_out_en = clk_in_en & ~clip_x & ~clip_y;

  wire [7:0]   y_out = y_in;
  wire [7:0]   cb_out = cb_in;
  wire [7:0]   cr_out = cr_in;

endmodule	// clip