rgb_fifo.v

一个视频信号输入的verilog源代码

	.clock(rdclk),
	.cnt_en(valid_rdreq),
	.q(wire_rdptr_g1p_q),
	.qbin()
	// synopsys translate_off
	,
	.clk_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	// synopsys translate_on
	);
	defparam
		rdptr_g1p.pvalue = 1,
		rdptr_g1p.width = 8,
		rdptr_g1p.lpm_type = "a_graycounter";
	a_graycounter   wrptr_g1p
	( 
	.aclr(aclr),
	.clock(wrclk),
	.cnt_en(valid_wrreq),
	.q(wire_wrptr_g1p_q),
	.qbin()
	// synopsys translate_off
	,
	.clk_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	// synopsys translate_on
	);
	defparam
		wrptr_g1p.pvalue = 1,
		wrptr_g1p.width = 8,
		wrptr_g1p.lpm_type = "a_graycounter";
	altsyncram   fifo_ram
	( 
	.address_a(wrptr_g),
	.address_b(((wire_rdptr_g_q & {8{int_rdempty}}) | (wire_rdptr_g1p_q & {8{(~ int_rdempty)}}))),
	.clock0(wrclk),
	.clock1(rdclk),
	.clocken1((valid_rdreq | int_rdempty)),
	.data_a(data),
	.q_a(),
	.q_b(wire_fifo_ram_q_b),
	.wren_a(valid_wrreq)
	// synopsys translate_off
	,
	.aclr0(1'b0),
	.aclr1(1'b0),
	.addressstall_a(),
	.addressstall_b(),
	.byteena_a(),
	.byteena_b(),
	.clocken0(1'b1),
	.data_b(18'b111111111111111111),
	.rden_b(1'b1),
	.wren_b(1'b0)
	// synopsys translate_on
	);
	defparam
		fifo_ram.address_reg_b = "CLOCK1",
		fifo_ram.operation_mode = "DUAL_PORT",
		fifo_ram.outdata_reg_b = "UNREGISTERED",
		fifo_ram.ram_block_type = "M4K",
		fifo_ram.width_a = 18,
		fifo_ram.width_b = 18,
		fifo_ram.width_byteena_a = 1,
		fifo_ram.widthad_a = 8,
		fifo_ram.widthad_b = 8,
		fifo_ram.intended_device_family = "Cyclone",
		fifo_ram.lpm_type = "altsyncram";
	// synopsys translate_off
	initial
		delayed_wrptr_g = 0;
	// synopsys translate_on
	always @ ( posedge wrclk or posedge aclr)
		if (aclr == 1'b1) delayed_wrptr_g <= 8'b0;
		else   delayed_wrptr_g <= wrptr_g;
	// synopsys translate_off
	initial
		wrptr_g = 0;
	// synopsys translate_on
	always @ ( posedge wrclk or posedge aclr)
		if (aclr == 1'b1) wrptr_g <= 8'b0;
		else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
	rgb_fifo_alt_synch_pipe_nm4   rs_dgwp
	( 
	.clock(rdclk),
	.clrn((~ aclr)),
	.d(delayed_wrptr_g),
	.q(wire_rs_dgwp_q));
	rgb_fifo_alt_synch_pipe_nm4   ws_dgrp
	( 
	.clock(wrclk),
	.clrn((~ aclr)),
	.d(wire_rdptr_g_q),
	.q(wire_ws_dgrp_q));
	always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
		if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
			begin
				wire_rdempty_eq_comp_aeb_int = 1'b1;
			end
		else
			begin
				wire_rdempty_eq_comp_aeb_int = 1'b0;
			end
	assign
		wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
	assign
		wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
		wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
	always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
		if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
			begin
				wire_wrfull_eq_comp_aeb_int = 1'b1;
			end
		else
			begin
				wire_wrfull_eq_comp_aeb_int = 1'b0;
			end
	assign
		wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
	assign
		wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
		wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
	assign
		int_rdempty = wire_rdempty_eq_comp_aeb,
		int_wrfull = wire_wrfull_eq_comp_aeb,
		q = wire_fifo_ram_q_b,
		rdempty = int_rdempty,
		valid_rdreq = (rdreq & (~ int_rdempty)),
		valid_wrreq = (wrreq & (~ int_wrfull)),
		wrfull = int_wrfull;
endmodule //rgb_fifo_dcfifo_drt
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rgb_fifo (
	data,
	wrreq,
	rdreq,
	rdclk,
	wrclk,
	aclr,
	q,
	rdempty)/* synthesis synthesis_clearbox = 1 */;

	input	[17:0]  data;
	input	  wrreq;
	input	  rdreq;
	input	  rdclk;
	input	  wrclk;
	input	  aclr;
	output	[17:0]  q;
	output	  rdempty;

	wire  sub_wire0;
	wire [17:0] sub_wire1;
	wire  rdempty = sub_wire0;
	wire [17:0] q = sub_wire1[17:0];

	rgb_fifo_dcfifo_drt	rgb_fifo_dcfifo_drt_component (
				.wrclk (wrclk),
				.rdreq (rdreq),
				.aclr (aclr),
				.rdclk (rdclk),
				.wrreq (wrreq),
				.data (data),
				.rdempty (sub_wire0),
				.q (sub_wire1));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "18"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: WIZMAN_OVERRIDE_CBX_GEN_MODE STRING "ON"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "data;rdclk;rdreq;wrclk;wrreq"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "aclr;q;rdempty;rdfull;wrempty"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "wrfull;rdusedw;wrusedw"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "TRUE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_wave*.jpg FALSE