rgb_fifo.v

一个视频信号输入的verilog源代码

// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo 

// ============================================================
// File Name: rgb_fifo.v
// Megafunction Name(s):
// 			dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
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//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.


//dcfifo ADD_RAM_OUTPUT_REGISTER=OFF CBX_AUTO_BLACKBOX=ON CLOCKS_ARE_SYNCHRONIZED=TRUE DEVICE_FAMILY=Cyclone LPM_NUMWORDS=256 LPM_SHOWAHEAD=ON LPM_WIDTH=18 LPM_WIDTHU=8 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=ON aclr data q rdclk rdempty rdreq wrclk wrreq lpm_hint=RAM_BLOCK_TYPE=M4K RAM_BLOCK_TYPE=M4K
//VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2004:02:27:16:26:10:SJ cbx_dcfifo 2004:02:27:10:24:02:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2004:02:27:10:23:48:SJ cbx_stratix 2004:02:27:16:26:40:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


//dffpipe CBX_AUTO_BLACKBOX=ON WIDTH=8 clock clrn d q
//VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2004:02:27:16:26:10:SJ cbx_dcfifo 2004:02:27:10:24:02:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2004:02:27:10:23:48:SJ cbx_stratix 2004:02:27:16:26:40:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


//dffpipe CBX_AUTO_BLACKBOX=ON WIDTH=8 clock clrn d q
//VERSION_BEGIN 4.0 cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END

//synthesis_resources = lut 8 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  rgb_fifo_dffpipe_nm4
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_INTERNAL_OPTION="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
	input   clock;
	input   clrn;
	input   [7:0]  d;
	output   [7:0]  q;

	wire	[7:0]	wire_dffe2a_D;
	reg	[7:0]	dffe2a;
	wire ena;
	wire prn;
	wire sclr;

	// synopsys translate_off
	initial
		dffe2a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[0:0] <= 1;
		else if (clrn == 1'b0) dffe2a[0:0] <= 0;
		else if  (ena == 1'b1)   dffe2a[0:0] <= wire_dffe2a_D[0:0];
	// synopsys translate_off
	initial
		dffe2a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[1:1] <= 1;
		else if (clrn == 1'b0) dffe2a[1:1] <= 0;
		else if  (ena == 1'b1)   dffe2a[1:1] <= wire_dffe2a_D[1:1];
	// synopsys translate_off
	initial
		dffe2a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[2:2] <= 1;
		else if (clrn == 1'b0) dffe2a[2:2] <= 0;
		else if  (ena == 1'b1)   dffe2a[2:2] <= wire_dffe2a_D[2:2];
	// synopsys translate_off
	initial
		dffe2a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[3:3] <= 1;
		else if (clrn == 1'b0) dffe2a[3:3] <= 0;
		else if  (ena == 1'b1)   dffe2a[3:3] <= wire_dffe2a_D[3:3];
	// synopsys translate_off
	initial
		dffe2a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[4:4] <= 1;
		else if (clrn == 1'b0) dffe2a[4:4] <= 0;
		else if  (ena == 1'b1)   dffe2a[4:4] <= wire_dffe2a_D[4:4];
	// synopsys translate_off
	initial
		dffe2a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[5:5] <= 1;
		else if (clrn == 1'b0) dffe2a[5:5] <= 0;
		else if  (ena == 1'b1)   dffe2a[5:5] <= wire_dffe2a_D[5:5];
	// synopsys translate_off
	initial
		dffe2a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[6:6] <= 1;
		else if (clrn == 1'b0) dffe2a[6:6] <= 0;
		else if  (ena == 1'b1)   dffe2a[6:6] <= wire_dffe2a_D[6:6];
	// synopsys translate_off
	initial
		dffe2a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe2a[7:7] <= 1;
		else if (clrn == 1'b0) dffe2a[7:7] <= 0;
		else if  (ena == 1'b1)   dffe2a[7:7] <= wire_dffe2a_D[7:7];
	assign
		wire_dffe2a_D = (d & {8{(~ sclr)}});
	assign
		ena = 1'b1,
		prn = 1'b1,
		q = dffe2a,
		sclr = 1'b0;
endmodule //rgb_fifo_dffpipe_nm4

//synthesis_resources = lut 8 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  rgb_fifo_alt_synch_pipe_nm4
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_INTERNAL_OPTION="X_ON_VIOLATION_OPTION=OFF" */;
	input   clock;
	input   clrn;
	input   [7:0]  d;
	output   [7:0]  q;

	wire  [7:0]   wire_dffpipe1_q;

	rgb_fifo_dffpipe_nm4   dffpipe1
	( 
	.clock(clock),
	.clrn(clrn),
	.d(d),
	.q(wire_dffpipe1_q));
	assign
		q = wire_dffpipe1_q;
endmodule //rgb_fifo_alt_synch_pipe_nm4


//lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 aeb dataa datab
//VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


//lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 aeb dataa datab
//VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END

//synthesis_resources = a_graycounter 3 altsyncram 1 lut 34 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  rgb_fifo_dcfifo_drt
	( 
	aclr,
	data,
	q,
	rdclk,
	rdempty,
	rdreq,
	wrclk,
	wrfull,
	wrreq) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_INTERNAL_OPTION="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
	input   aclr;
	input   [17:0]  data;
	output   [17:0]  q;
	input   rdclk;
	output   rdempty;
	input   rdreq;
	input   wrclk;
	output   wrfull;
	input   wrreq;

	wire  [7:0]   wire_rdptr_g_q;
	wire  [7:0]   wire_rdptr_g1p_q;
	wire  [7:0]   wire_wrptr_g1p_q;
	wire  [17:0]   wire_fifo_ram_q_b;
	reg	[7:0]	delayed_wrptr_g;
	reg	[7:0]	wrptr_g;
	wire  [7:0]   wire_rs_dgwp_q;
	wire  [7:0]   wire_ws_dgrp_q;
	reg	wire_rdempty_eq_comp_aeb_int;
	wire	wire_rdempty_eq_comp_aeb;
	wire	[7:0]	wire_rdempty_eq_comp_dataa;
	wire	[7:0]	wire_rdempty_eq_comp_datab;
	reg	wire_wrfull_eq_comp_aeb_int;
	wire	wire_wrfull_eq_comp_aeb;
	wire	[7:0]	wire_wrfull_eq_comp_dataa;
	wire	[7:0]	wire_wrfull_eq_comp_datab;
	wire  int_rdempty;
	wire  int_wrfull;
	wire  valid_rdreq;
	wire  valid_wrreq;

	a_graycounter   rdptr_g
	( 
	.aclr(aclr),
	.clock(rdclk),
	.cnt_en(valid_rdreq),
	.q(wire_rdptr_g_q),
	.qbin()
	// synopsys translate_off
	,
	.clk_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	// synopsys translate_on
	);
	defparam
		rdptr_g.width = 8,
		rdptr_g.lpm_type = "a_graycounter";
	a_graycounter   rdptr_g1p
	( 
	.aclr(aclr),