avalon_register_slave.v

一个视频信号输入的verilog源代码

// ================================================================================
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// ================================================================================
// Avalon register slave module for automotive demo system video in module.
//
// This version assumes video in module is connected to Avalon clock and so no
// synchronisation is neccessary between the avalon and the video clock domain.
// ================================================================================
`timescale 1ns/1ns

module avalon_register_slave
  (
   clk,
   reset_n,

   // Avalon slave
   s_address,
   s_chipselect,
   s_read_n,
   s_write_n,
   s_writedata,
   s_readdata,

   irq,

   // Control/status
   cb_sel,
   
   // Camera module
   camxlen_reg,
   
   // Clipping
   xclips_reg,
   xclipe_reg,
   yclips_reg,
   yclipe_reg,
   
   // Scaling
   xscale_reg,
   yscale_reg,
   xlen_reg,
   ylen_reg,

   // DMA Write Master
   wr_mcontrol,
   m_enable_bit,
   fb_done,
   mfb_reg
   );

  input clk;
  input reset_n;
  
  // Avalon slave
  input [4:0] s_address;
  input       s_chipselect;
  input       s_read_n;
  input       s_write_n;
  input [31:0] s_writedata;
  output [31:0] s_readdata;

  output 	irq;

  // Control/status
  output 	cb_sel;
				       
  // Camera module
  output [9:0] 	camxlen_reg;

  // Clipping
  output [9:0] 	xclips_reg;
  output [9:0] 	xclipe_reg;
  output [8:0] 	yclips_reg;
  output [8:0] 	yclipe_reg;

  // Scaling
  output [15:0] xscale_reg;
  output [15:0] yscale_reg;
  output [9:0] 	xlen_reg;
  output [8:0] 	ylen_reg;
  
  // DMA Write Master
  output 	wr_mcontrol;
  output 	m_enable_bit;
  input 	fb_done;
  output [31:0] mfb_reg;

  reg [1:0]	control_reg;		
  reg [9:0] 	camxlen_reg;
  reg [9:0] 	xclips_reg;
  reg [9:0] 	xclipe_reg;
  reg [8:0] 	yclips_reg;
  reg [8:0] 	yclipe_reg;
  reg [15:0] 	xscale_reg;
  reg [9:0] 	xlen_reg;
  reg [15:0] 	yscale_reg;
  reg [8:0] 	ylen_reg;
  reg [31:0] 	mcontrol_reg;
  reg [3:0] 	minten_reg;
  reg [31:0] 	mfb_reg;

//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
  wire 		control_sel = (s_address == (7'h00>>2));
  wire 		camxlen_sel = (s_address == (7'h10>>2));
  wire 		xclips_sel = (s_address == (7'h20>>2));
  wire 		xclipe_sel = (s_address == (7'h24>>2));
  wire 		yclips_sel = (s_address == (7'h28>>2));
  wire 		yclipe_sel = (s_address == (7'h2c>>2));
  wire 		xscale_sel = (s_address == (7'h30>>2));
  wire 		xlen_sel = (s_address == (7'h34>>2));
  wire 		yscale_sel = (s_address == (7'h38>>2));
  wire 		ylen_sel = (s_address == (7'h3c>>2));
  wire 		mcontrol_sel = (s_address == (7'h40>>2));
  wire 		mstat_sel = (s_address == (7'h40>>2));
  wire 		minten_sel = (s_address == (7'h44>>2));
  wire 		micr_sel = (s_address == (7'h48>>2));
  wire 		mfb_sel = (s_address == (7'h50>>2));
  
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      control_reg <= 2'b0;
    else if (s_chipselect & ~s_write_n & control_sel)
      control_reg <= s_writedata[1:0];

  wire 		cb_sel = control_reg[0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      camxlen_reg <= 10'b0;
    else if (s_chipselect & ~s_write_n & camxlen_sel)
      camxlen_reg <= s_writedata[9:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      xclips_reg <= 10'b0;
    else if (s_chipselect & ~s_write_n & xclips_sel)
      xclips_reg <= s_writedata[9:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      xclipe_reg <= 10'b0;
    else if (s_chipselect & ~s_write_n & xclipe_sel)
      xclipe_reg <= s_writedata[9:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      yclips_reg <= 9'b0;
    else if (s_chipselect & ~s_write_n & yclips_sel)
      yclips_reg <= s_writedata[8:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      yclipe_reg <= 9'b0;
    else if (s_chipselect & ~s_write_n & yclipe_sel)
      yclipe_reg <= s_writedata[8:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      xscale_reg <= 16'b0;
    else if (s_chipselect & ~s_write_n & xscale_sel)
      xscale_reg <= s_writedata[15:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      xlen_reg <= 10'b0;
    else if (s_chipselect & ~s_write_n & xlen_sel)
      xlen_reg <= s_writedata[9:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      yscale_reg <= 16'b0;
    else if (s_chipselect & ~s_write_n & yscale_sel)
      yscale_reg <= s_writedata[15:0];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      ylen_reg <= 9'b0;
    else if (s_chipselect & ~s_write_n & ylen_sel)
      ylen_reg <= s_writedata[8:0];

  wire wr_mcontrol = s_chipselect & ~s_write_n & mcontrol_sel;
  
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      mcontrol_reg <= 32'b0;
    else if (wr_mcontrol)
      mcontrol_reg <= s_writedata[31:0];

  wire 		m_enable_bit = mcontrol_reg[0];

  wire [3:0] 	mstat = {fb_done, mcontrol_reg[2:0]};

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      minten_reg <= 9'b0;
    else if (s_chipselect & ~s_write_n & minten_sel)
      minten_reg <= s_writedata[3:0];

  wire 		fb_inten = minten_reg[3];

  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      mfb_reg <= 32'b0;
    else if (s_chipselect & ~s_write_n & mfb_sel)
      mfb_reg <= s_writedata[31:0];

  reg  fb_done_r;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      fb_done_r <= 1'b0;
    else
      fb_done_r <= fb_done;

  reg  irq;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      irq <= 1'b0;
    else if (fb_done & ~fb_done_r & fb_inten)
      irq <= 1'b1;
    else if (s_chipselect & ~s_write_n & micr_sel & s_writedata[3])
      irq <= 1'b0;
  
  wire [31:0] s_readdata = 32'b0
			 | {2{camxlen_sel}} & control_reg
			 | {10{camxlen_sel}} & camxlen_reg
			 | {10{xclips_sel}} & xclips_reg
			 | {10{xclipe_sel}} & xclipe_reg
			 | {9{yclips_sel}} & yclips_reg
			 | {9{yclipe_sel}} & yclipe_reg
			 | {16{xscale_sel}} & xscale_reg
			 | {10{xlen_sel}} & xlen_reg
			 | {16{yscale_sel}} & yscale_reg
			 | {9{ylen_sel}} & ylen_reg
			 | {4{mstat_sel}} & mstat
			 | {4{minten_sel}} & minten_reg
			 | {4{micr_sel}} & {irq, 3'b0}
			 | {32{mfb_sel}} & mfb_reg;
  
endmodule	// avalon_register_slave