camera_gray_count.v

一个视频信号输入的verilog源代码

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//----------------------------------------------------------------------------------------------------------------------
// parameterizable gray code counter with synchronous enable.
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
       
module camera_gray_count
  (
   clk,
   reset_n,
   en,
   
   gray,
   binary,
   next_gray,
   next_binary
   );
  
  parameter WIDTH = 2;

  input clk;
  input reset_n;
  input en;

  output [WIDTH-1:0] gray;
  output [WIDTH-1:0] binary;
  output [WIDTH-1:0] next_gray;
  output [WIDTH-1:0] next_binary;

  reg [WIDTH-1:0]    binary;
  reg [WIDTH-1:0]    gray;

  // next_binary and next_gray anticipate the codes. These are combinatorial
  // function of the binary count and so may have multiple bits toggling.
  wire [WIDTH-1:0]   next_binary = binary + {{WIDTH-1{1'b0}}, 1'b1};

  wire [WIDTH-1:0]   next_gray = next_binary ^ (next_binary>>1);

  // gray output is registered from next_grey so as to guarantee only one bit will
  // change. this allows it to be passed between clock domains and still be sampled
  // as either the old or new value
  always @(posedge clk or negedge reset_n)
  begin
    if (~reset_n)
    begin
      gray <= {WIDTH{1'b0}};
      binary <= {WIDTH{1'b0}};
    end
    else if (en)
    begin
      gray <= next_gray;
      binary <= next_binary;
    end
  end

endmodule // camera_gray_count