colour_bars.v

一个视频信号输入的verilog源代码

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//---------------------------------------------------------------------------
// Test harness for Auto demo system video-in module
//---------------------------------------------------------------------------
`timescale 1ps/1ps

module colour_bars (
		    clk,
		    reset_n,
		    
		    // Camera input
		    cam_clk,
		    cam_hsync,
		    cam_vsync,
		    cam_d
		    );

  input clk;
  input reset_n;

  output cam_clk;
  output cam_hsync;
  output cam_vsync;
  output [7:0] cam_d;

  reg [10:0]    pixel;
  reg [8:0]    line;

  always @(negedge clk or negedge reset_n)
    if (~reset_n)
      pixel <= 11'b0;
    else if (pixel == 11'd1691)
      pixel <= 11'b0;
    else
      pixel <= pixel + 11'd1;

  always @(negedge clk or negedge reset_n)
    if (~reset_n)
      line <= 9'd490;
    else if ((pixel == 11'd1691) & (line == 9'd511))
      line <= 9'd0;
    else if (pixel == 11'd1691)
      line <= line + 9'd1;

  reg 	       cam_clk_en;
  always @(negedge clk or negedge reset_n)
    if (~reset_n)
      cam_clk_en <= 0;
    else if (pixel == 11'd1279)
      // end of line
      cam_clk_en <= 1'b0;
    else if ((pixel == 11'd1691) & ((line < 9'd479) | (line == 9'd511)))
      // start of new active line
      cam_clk_en <= 1'b1;

  wire 	       cam_clk = clk & cam_clk_en;

  reg 	       cam_vsync;
  always @(negedge clk or negedge reset_n)
    if (~reset_n)
      cam_vsync <= 1'b0;
    else if ((pixel == 11'd1691) & (line == 9'd511))
      // Start of new frame
      cam_vsync <= 1'b1;
    else if ((pixel == 11'd1279) & (line == 9'd479))
      // End of frame
      cam_vsync <= 1'b0;

  wire 	       cam_hsync = cam_clk_en;

  // YCbCr values calculated assuming gamma corrected RGB with 0 - 255 range
  reg [31:0]    colour;
  wire [31:0] 	white = {8'd128, 8'd235, 8'd128, 8'd235};
  wire [31:0] 	yellow = {8'd16, 8'd210, 8'd146, 8'd210};
  wire [31:0] 	cyan = {8'd166, 8'd170, 8'd16, 8'd170};
  wire [31:0] 	green = {8'd54, 8'd145, 8'd34, 8'd145};
  wire [31:0] 	magenta = {8'd202, 8'd107, 8'd222, 8'd107};
  wire [31:0] 	red = {8'd90, 8'd82, 8'd240, 8'd82};
  wire [31:0] 	blue = {8'd240, 8'd41, 8'd110, 8'd41};
  wire [31:0] 	black = {8'd128, 8'd16, 8'd128, 8'd16};
  
  always @(pixel or white or yellow or cyan or green
	   or magenta or red or blue or black)
    case (pixel[10:7])
      4'h0:	colour = white;
      4'h1:	colour = yellow;
      4'h2:	colour = cyan;
      4'h3:	colour = green;
      4'h4:	colour = magenta;
      4'h5:	colour = red;
      4'h6:	colour = blue;
      4'h7:	colour = black;
      4'h8:	colour = white;
      4'h9:	colour = yellow;
      default:	colour = cyan;
    endcase

  reg [7:0] 	cam_d;
  always @(pixel or colour)
    case (pixel[1:0])
      2'b00:	cam_d <= colour[31:24];
      2'b01:	cam_d <= colour[23:16];
      2'b10:	cam_d <= colour[15:8];
      default:	cam_d <= colour[7:0];
    endcase

endmodule