videoin.v

一个视频信号输入的verilog源代码

// ================================================================================
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// Altera products are protected under numerous U.S. and foreign patents, maskwork
// rights, copyrights and other intellectual property laws.
// 
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design License
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// file and please promptly destroy any copies you have made.
// 
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
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// warranties of merchantability, non-infringement, or fitness for a particular
// purpose, are specifically disclaimed.  By making this reference design file
// available, Altera expressly does not recommend, suggest or require that this
// reference design file be used in combination with any other product not
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// ================================================================================
//---------------------------------------------------------------------------
// Top level wrapper for video in component
//---------------------------------------------------------------------------
`timescale 1ps/1ps

module videoin (
		reset_n,
		clk_nios,
		clk_video,
		clk_cam,

		// camera interface
		cam_clk,
		cam_din,
		cam_hsync,
		cam_vsync,

		// Avalon DMA register slave
		s_address,
		s_chipselect,
		s_read_n,
		s_write_n,
		s_writedata,
		s_readdata,

		irq,
		
		// Avalon DMA master
		m_address,
		m_write_n,
		m_writedata,
		m_waitrequest
		);

  input reset_n;
  input clk_nios;
  input clk_video;
  input clk_cam;
  
		// camera interface
  input cam_clk;
  input [7:0] cam_din;
  input       cam_hsync;
  input       cam_vsync;

   // Avalon DMA register slave
  input [4:0]   s_address;
  input         s_chipselect;
  input         s_read_n;
  input         s_write_n;
  input [31:0]  s_writedata;
  output [31:0] s_readdata;

  output 	irq;

   // Avalon DMA master
  output [31:0] m_address;
  output 	m_write_n;
  output [31:0] m_writedata;
  input 	m_waitrequest;

  // 656 rx module
  wire 		clk_135_en;
  wire 		sof;
  wire [9:0] 	pixel;
  wire [8:0] 	line;
  wire [7:0] 	y_in;
  wire [7:0] 	cb_in;
  wire [7:0] 	cr_in;
  wire 		frame_sync;

  // clipping
  wire 		clipped_clk_en;
  wire [7:0] 	clipped_y;
  wire [7:0] 	clipped_cb;
  wire [7:0] 	clipped_cr;

  // CSC
  wire [5:0] 	red_in;
  wire [5:0] 	green_in;
  wire [5:0] 	blue_in;

  // RGB FIFO
  wire 		rgb_empty;
  wire [17:0] 	rgb_rdata;

  // Y scaling
  wire 		rgb_rd;
  wire [17:0] 	rgb_y_scaled;
  wire 		rgb_y_en;
  wire 		y_eof;
  
  // X scaling
  wire [17:0] 	rgb_x_scaled;
  wire 		rgb_x_en;
  wire 		eol;
  wire 		x_eof;

  // Pixel packing
  wire 		rgb_packed_en;
  wire [31:0] 	rgb_packed;
  wire 		pack_eof;
  
   // Avalon DMA register slave
  wire 		cb_sel;
  wire [9:0] 	camxlen_reg;
  wire [9:0] 	xclips_reg;
  wire [9:0] 	xclipe_reg;
  wire [8:0] 	yclips_reg;
  wire [8:0] 	yclipe_reg;
  wire [15:0] 	yscale_reg;
  wire [15:0] 	xscale_reg;
  wire [9:0] 	xlen_reg;
  wire [8:0] 	ylen_reg;
  wire 		wr_mcontrol;
  wire 		irq;

  // DMA Write Master
  wire 		m_enable_bit;
  wire 		fb_done;
  wire [31:0] 	mfb_reg;

  wire 		cb_clk;
  wire 		cb_hsync;
  wire 		cb_vsync;
  wire [7:0] 	cb_d;
  
//---------------------------------------------------------------------------
// Instantiate colour bars module
//---------------------------------------------------------------------------
colour_bars u_colour_bars (
			   .clk		(clk_cam),
			   .reset_n	(reset_n),
			   
			   // Camera input
			   .cam_clk	(cb_clk),
			   .cam_hsync	(cb_hsync),
			   .cam_vsync	(cb_vsync),
			   .cam_d	(cb_d)
			   );

  wire 		mux_cam_clk = cb_sel ? cb_clk : cam_clk;
  wire 		mux_hsync = cb_sel ? cb_hsync : cam_hsync;
  wire 		mux_vsync = cb_sel ? cb_vsync : cam_vsync;
  wire [7:0] 	mux_cam_d = cb_sel ? cb_d : cam_din;
  
//---------------------------------------------------------------------------
// Instantiate camera input module
//---------------------------------------------------------------------------
  camera u_camera (
		   .clk		(clk_cam),
		   .reset_n	(reset_n),
		   
		   // Camera input
		   .cam_clk	(mux_cam_clk),
		   .cam_hsync	(mux_hsync),
		   .cam_vsync	(mux_vsync),
		   .cam_din	(mux_cam_d),

		   .camxlen	(camxlen_reg),
		   
		   // Outputs
		   .clk_out_en	(clk_135_en),
		   .sof		(sof),
		   .pixel	(pixel),
		   .line	(line),
		   .y		(y_in),
		   .cb		(cb_in),
		   .cr		(cr_in)
		   );

//---------------------------------------------------------------------------
// Instantiate clipping
//---------------------------------------------------------------------------
  clip u_clip (
	       .clk		(clk_cam),
	       
	       // input samples and timing
	       .clk_in_en	(clk_135_en),
	       .y_in		(y_in),
	       .cb_in		(cb_in),
	       .cr_in		(cr_in),
	       .pixel		(pixel),
	       .line		(line),
	       
	       // output samples
	       .clk_out_en	(clipped_clk_en),
	       .y_out		(clipped_y),
	       .cb_out		(clipped_cb),
	       .cr_out		(clipped_cr),
	       
	       // clipping registers
	       .xclips		(xclips_reg),
	       .xclipe		(xclipe_reg),
	       .yclips		(yclips_reg),
	       .yclipe		(yclipe_reg)
	       );

//---------------------------------------------------------------------------
// Instantiate colour space converter
//---------------------------------------------------------------------------
  csc u_csc (
	     .y		(clipped_y),
	     .cb	(clipped_cb),
	     .cr	(clipped_cr),

	     .r		(red_in),
	     .g		(green_in),
	     .b		(blue_in)
	     );
  
//---------------------------------------------------------------------------
// Instantiate RGB input FIFO
//---------------------------------------------------------------------------
  rgb_fifo u_rgb_fifo (
		       .aclr	(~reset_n | sof),
		       
		       .wrclk	(clk_cam),
		       .wrreq	(clipped_clk_en),
		       .data	({red_in, green_in, blue_in}),
		       
		       .rdclk	(clk_video),
		       .rdreq	(rgb_rd),
		       .q	(rgb_rdata),
		       .rdempty	(rgb_empty)
		       );
  
//---------------------------------------------------------------------------
// Instantiate Y scaling
//---------------------------------------------------------------------------
  yscale u_yscale (
		   .clk		(clk_video),
		   .reset_n	(~(~reset_n | sof)),

		   // input
		   .rgb_empty	(rgb_empty),
		   .rgb_rd	(rgb_rd),
		   .rgb_in	(rgb_rdata),
		   
		   // output
		   .rgb_out	(rgb_y_scaled),
		   .rgb_out_en	(rgb_y_en),
		   .eof		(y_eof),
		   
		   // control registers
		   .yscale_reg	(yscale_reg),
		   .xlen	(xlen_reg),
		   .ylen	(ylen_reg)
		   );

//---------------------------------------------------------------------------
// Instantiate X scaling
//---------------------------------------------------------------------------
  xscale u_xscale (
		   .clk		(clk_video),
		   .reset_n	(~(~reset_n | sof)),

		   .eof_in	(y_eof),

		   // input
		   .rgb_in_en	(rgb_y_en),
		   .rgb_in	(rgb_y_scaled),

		   // output
		   .rgb_out_en	(rgb_x_en),
		   .rgb_out	(rgb_x_scaled),
		   .eol		(eol),
		   .eof		(x_eof),

		   // control registers
		   .xscale_reg	(xscale_reg),
		   .xlen	(xlen_reg)
		   );
  
//---------------------------------------------------------------------------
// Instantiate Logic to pack pixels to 565 format, two pixels per word
//---------------------------------------------------------------------------
  pack565 u_pack565 (
		     .clk		(clk_video),
		     .reset_n		(~(~reset_n | sof)),
		     
		     // Input
		     .rgb_x_en		(rgb_x_en),
		     .rgb_x_scaled	(rgb_x_scaled),
		     .eof_in		(x_eof),

		     // output
		     .rgb_packed_en	(rgb_packed_en),
		     .rgb_packed	(rgb_packed),
		     .eof		(pack_eof)
		     );
  
//---------------------------------------------------------------------------
// Instantiate Avalon write DMA FIFO
//---------------------------------------------------------------------------
  avalon_wr_dma_fifo u_avalon_mast (
				    .clk_f		(clk_video),
				    .clk_av		(clk_nios),
				    .reset_n		(reset_n),
				    .sof		(sof),
				    
				    // FIFO write interface
				    .wr			(rgb_packed_en),
				    .wdata		(rgb_packed),
				    .full		(),
				    .eof_in		(pack_eof),

				    // Registers
				    .wr_mcontrol	(wr_mcontrol),
				    .m_enable_bit	(m_enable_bit),
				    .fb_done		(fb_done),
				    .mfb_reg		(mfb_reg),
				    
				    // Avalon DMA master
				    .m_address		(m_address),
				    .m_write_n		(m_write_n),
				    .m_writedata	(m_writedata),
				    .m_waitrequest	(m_waitrequest)
				    );

//---------------------------------------------------------------------------
// Instantiate Avalon slave
//---------------------------------------------------------------------------
  avalon_register_slave u_avalon_regs (
				       .clk		(clk_nios),
				       .reset_n		(reset_n),

				       // Avalon slave
				       .s_address	(s_address),
				       .s_chipselect	(s_chipselect),
				       .s_read_n	(s_read_n),
				       .s_write_n	(s_write_n),
				       .s_writedata	(s_writedata),
				       .s_readdata	(s_readdata),

				       .irq		(irq),

				       // Control/Status
				       .cb_sel		(cb_sel),
				       
				       // Camera module
				       .camxlen_reg	(camxlen_reg),

				       // Clipping
				       .xclips_reg	(xclips_reg),
				       .xclipe_reg	(xclipe_reg),
				       .yclips_reg	(yclips_reg),
				       .yclipe_reg	(yclipe_reg),

				       // Scaling
				       .xscale_reg	(xscale_reg),
				       .yscale_reg	(yscale_reg),
				       .xlen_reg	(xlen_reg),
				       .ylen_reg	(ylen_reg),

				       // DMA Write Master
				       .wr_mcontrol	(wr_mcontrol),
				       .m_enable_bit	(m_enable_bit),
				       .fb_done		(fb_done),
				       .mfb_reg		(mfb_reg)
				       );
				    

endmodule