class.ptf

一个视频信号输入的verilog源代码

                              vhdl_record_type = "";
                           }
                           PORT m_writedata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT m_waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT reset_n
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset_n";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "avalon_wr_dma_fifo";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER device
                        {
                           parameter_name = "DEVICE";
                           type = "integer";
                           default_value = "Cyclone";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER idle
                        {
                           parameter_name = "idle";
                           type = "integer";
                           default_value = "4'b0000";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER wr1
                        {
                           parameter_name = "wr1";
                           type = "integer";
                           default_value = "4'b1000";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER wr2
                        {
                           parameter_name = "wr2";
                           type = "integer";
                           default_value = "4'b1001";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER wr3
                        {
                           parameter_name = "wr3";
                           type = "integer";
                           default_value = "4'b1010";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER write
                        {
                           parameter_name = "write";
                           type = "integer";
                           default_value = "4'b1100";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER wr_wait
                        {
                           parameter_name = "wr_wait";
                           type = "integer";
                           default_value = "4'b0100";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE bt656_rx.v
         {
            file_mod = "Mon Dec 13 09:23:16 CST 2004";
            quartus_map_start = "Tue Sep 12 17:44:10 CST 2006";
            quartus_map_finished = "Tue Sep 12 17:45:17 CST 2006";
            #found 1 valid modules
            WRAPPER bt656_rx
            {
               CLASS bt656_rx
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "D:/altera_6/reference_designs/auto_graphics_ref_design/32bit/altera_avalon_videoin/bt656_rx.v";
                        }
                     }
                     top_module_name = "bt656_rx";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "bt656_rx";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT din
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT clk_135_en
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT v_blank
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT field
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT pixel
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT line
                           {
                              width = "9";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT y
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT cb
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT cr
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                        PORT reset_n
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset_n";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "bt656_rx";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER idle
                        {
                           parameter_name = "idle";
                           type = "integer";
                           default_value = "2'b00";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER ff
                        {
                           parameter_name = "ff";
                           type = "integer";
                           default_value = "2'b01";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER ff00
                        {
                           parameter_name = "ff00";
                           type = "integer";
                           default_value = "2'b10";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER ff0000
                        {
                           parameter_name = "ff0000";
                           type = "integer";
                           default_value = "2'b11";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE camera.v
         {
            file_mod = "Mon Dec 13 09:23:16 CST 2004";
            quartus_map_start = "Tue Sep 12 17:45:17 CST 2006";
            quartus_map_finished = "Tue Sep 12 17:45:23 CST 2006";
            #found 1 valid modules
            WRAPPER camera
            {
               CLASS camera
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "D:/altera_6/reference_designs/auto_graphics_ref_design/32bit/altera_avalon_videoin/camera.v";
                        }
                     }
                     top_module_name = "camera";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {