class.ptf

一个视频信号输入的verilog源代码

               width_expression = "";
               direction = "input";
               type = "write_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT s_writedata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT s_readdata
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
      MASTER write_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "2";
            Has_Clock = "1";
            Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "0";
            Is_Writable = "1";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "0";
               stream_writes = "0";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT reset_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "reset_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT clk_nios
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "clk";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT m_address
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT m_write_n
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "write_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT m_writedata
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT m_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "video input";
         technology = "tenglong";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "video input - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_s1 = "SLAVE s1/SYSTEM_BUILDER_INFO";
            SBI_write_master = "MASTER write_master/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>video input 1.0   Built by tenglong</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2006.09.13.11:19:02";
               }
               TEXT 
               {
                  title = "Class name: video_input";
               }
               TEXT 
               {
                  title = "Class version: 1.0   Built by tenglong";
               }
               TEXT 
               {
                  title = "Component name: video input";
               }
               TEXT 
               {
                  title = "Component Group: Other";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "6.00";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES 
      {
         FILE 
         {
            filepath = "inc/camera.c";
            type = "Registers (inc/)";
         }
         FILE 
         {
            filepath = "inc/camera.h";
            type = "Registers (inc/)";
         }
         FILE 
         {
            filepath = "inc/videoin.c";
            type = "Registers (inc/)";
         }
         FILE 
         {
            filepath = "inc/videoin.h";
            type = "Registers (inc/)";
         }
      }
      built_on = "2006.09.13.11:19:02";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE avalon_register_slave.v
         {
            file_mod = "Mon Dec 13 09:23:16 CST 2004";
            quartus_map_start = "Tue Sep 12 17:43:42 CST 2006";
            quartus_map_finished = "Tue Sep 12 17:43:56 CST 2006";
            #found 1 valid modules
            WRAPPER avalon_register_slave
            {
               CLASS avalon_register_slave
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "D:/altera_6/reference_designs/auto_graphics_ref_design/32bit/altera_avalon_videoin/avalon_register_slave.v";
                        }
                     }
                     top_module_name = "avalon_register_slave";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "avalon_register_slave";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE s
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT s_address
                           {
                              width = "5";
                              width_expression = "";
                              direction = "input";
                              type = "address";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT s_chipselect
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "chipselect";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT s_read_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT s_write_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT s_writedata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "writedata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT s_readdata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "readdata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT irq
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "irq";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT cb_sel
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT camxlen_reg
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";