elec_lock.tan.qmsg

本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_4M SEGOUT\[1\] ACC\[14\] 50.500 ns register " "Info: tco from clock \"CLK_4M\" to destination pin \"SEGOUT\[1\]\" through register \"ACC\[14\]\" is 50.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 20.700 ns + Longest register " "Info: + Longest clock path from clock \"CLK_4M\" to source register is 20.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B1 41 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B1; Fanout = 41; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.600 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(1.100 ns) 12.900 ns N\[3\] 3 REG LC3_A6 2 " "Info: 3: + IC(5.400 ns) + CELL(1.100 ns) = 12.900 ns; Loc. = LC3_A6; Fanout = 2; REG Node = 'N\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.500 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.300 ns) 18.100 ns FN~27 4 COMB LC4_A17 20 " "Info: 4: + IC(2.900 ns) + CELL(2.300 ns) = 18.100 ns; Loc. = LC4_A17; Fanout = 20; COMB Node = 'FN~27'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.200 ns" { N[3] FN~27 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 20.700 ns ACC\[14\] 5 REG LC8_A16 5 " "Info: 5: + IC(2.600 ns) + CELL(0.000 ns) = 20.700 ns; Loc. = LC8_A16; Fanout = 5; REG Node = 'ACC\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.600 ns" { FN~27 ACC[14] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns ( 35.27 % ) " "Info: Total cell delay = 7.300 ns ( 35.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.400 ns ( 64.73 % ) " "Info: Total interconnect delay = 13.400 ns ( 64.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[14] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.700 ns + Longest register pin " "Info: + Longest register to pin delay is 28.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ACC\[14\] 1 REG LC8_A16 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A16; Fanout = 5; REG Node = 'ACC\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { ACC[14] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 6.000 ns DB\[2\]~124 2 COMB LC5_B2 1 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 6.000 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'DB\[2\]~124'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.000 ns" { ACC[14] DB[2]~124 } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 8.900 ns DB\[2\]~125 3 COMB LC2_B2 10 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 8.900 ns; Loc. = LC2_B2; Fanout = 10; COMB Node = 'DB\[2\]~125'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.900 ns" { DB[2]~124 DB[2]~125 } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(2.300 ns) 15.400 ns rtl~3 4 COMB LC7_C17 2 " "Info: 4: + IC(4.200 ns) + CELL(2.300 ns) = 15.400 ns; Loc. = LC7_C17; Fanout = 2; COMB Node = 'rtl~3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.500 ns" { DB[2]~125 rtl~3 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 18.300 ns SEG~448 5 COMB LC2_C17 2 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 18.300 ns; Loc. = LC2_C17; Fanout = 2; COMB Node = 'SEG~448'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.900 ns" { rtl~3 SEG~448 } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 21.200 ns SEG~449 6 COMB LC3_C17 1 " "Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 21.200 ns; Loc. = LC3_C17; Fanout = 1; COMB Node = 'SEG~449'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.900 ns" { SEG~448 SEG~449 } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 28.700 ns SEGOUT\[1\] 7 PIN PIN_28 0 " "Info: 7: + IC(2.400 ns) + CELL(5.100 ns) = 28.700 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'SEGOUT\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "7.500 ns" { SEG~449 SEGOUT[1] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.600 ns ( 57.84 % ) " "Info: Total cell delay = 16.600 ns ( 57.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.100 ns ( 42.16 % ) " "Info: Total interconnect delay = 12.100 ns ( 42.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "28.700 ns" { ACC[14] DB[2]~124 DB[2]~125 rtl~3 SEG~448 SEG~449 SEGOUT[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "28.700 ns" { ACC[14] DB[2]~124 DB[2]~125 rtl~3 SEG~448 SEG~449 SEGOUT[1] } { 0.000ns 3.700ns 0.600ns 4.200ns 0.600ns 0.600ns 2.400ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[14] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "28.700 ns" { ACC[14] DB[2]~124 DB[2]~125 rtl~3 SEG~448 SEG~449 SEGOUT[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "28.700 ns" { ACC[14] DB[2]~124 DB[2]~125 rtl~3 SEG~448 SEG~449 SEGOUT[1] } { 0.000ns 3.700ns 0.600ns 4.200ns 0.600ns 0.600ns 2.400ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK_4M SELOUT\[0\] lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 12.500 ns register " "Info: Minimum tco from clock \"CLK_4M\" to destination pin \"SELOUT\[0\]\" through register \"lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" is 12.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_4M\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_B1 23 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_B1; Fanout = 23; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.500 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.300 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_B1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B1; Fanout = 23; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 6.100 ns SELOUT\[0\] 2 PIN PIN_11 0 " "Info: 2: + IC(1.000 ns) + CELL(5.100 ns) = 6.100 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'SELOUT\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.100 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] SELOUT[0] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 83.61 % ) " "Info: Total cell delay = 5.100 ns ( 83.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.39 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.100 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] SELOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.100 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] SELOUT[0] } { 0.000ns 1.000ns } { 0.000ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.300 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.100 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[4] SELOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Techno