elec_lock.tan.qmsg

来自「本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "FN~27 " "Info: Detected gated clock \"FN~27\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FN~27" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "N\[2\] " "Info: Detected ripple clock \"N\[2\]\" as buffer" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "N\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "N\[3\] " "Info: Detected ripple clock \"N\[3\]\" as buffer" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "N\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "N\[1\] " "Info: Detected ripple clock \"N\[1\]\" as buffer" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "N\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "N\[0\] " "Info: Detected ripple clock \"N\[0\]\" as buffer" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "N\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] " "Info: Detected ripple clock \"lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}