elec_lock.tan.qmsg

本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块

{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_4M register ACC\[15\] register QA 222.9 ns " "Info: Slack time is 222.9 ns for clock \"CLK_4M\" between source register \"ACC\[15\]\" and destination register \"QA\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "36.9 MHz 27.1 ns " "Info: Fmax is 36.9 MHz (period= 27.1 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "237.500 ns + Largest register register " "Info: + Largest register to register requirement is 237.500 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "250.000 ns + " "Info: + Setup relationship between source and destination is 250.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 250.000 ns " "Info: + Latch edge is 250.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_4M 250.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK_4M\" is 250.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_4M 250.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK_4M\" is 250.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.900 ns + Largest " "Info: + Largest clock skew is -8.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M destination 11.800 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_4M\" to destination register is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B1 41 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B1; Fanout = 41; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.600 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(0.000 ns) 11.800 ns QA 3 REG LC3_A13 2 " "Info: 3: + IC(5.400 ns) + CELL(0.000 ns) = 11.800 ns; Loc. = LC3_A13; Fanout = 2; REG Node = 'QA'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.400 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 33.05 % ) " "Info: Total cell delay = 3.900 ns ( 33.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 66.95 % ) " "Info: Total interconnect delay = 7.900 ns ( 66.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 20.700 ns - Longest register " "Info: - Longest clock path from clock \"CLK_4M\" to source register is 20.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B1 41 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B1; Fanout = 41; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.600 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(1.100 ns) 12.900 ns N\[3\] 3 REG LC3_A6 2 " "Info: 3: + IC(5.400 ns) + CELL(1.100 ns) = 12.900 ns; Loc. = LC3_A6; Fanout = 2; REG Node = 'N\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.500 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.300 ns) 18.100 ns FN~27 4 COMB LC4_A17 20 " "Info: 4: + IC(2.900 ns) + CELL(2.300 ns) = 18.100 ns; Loc. = LC4_A17; Fanout = 20; COMB Node = 'FN~27'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.200 ns" { N[3] FN~27 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 20.700 ns ACC\[15\] 5 REG LC6_A16 5 " "Info: 5: + IC(2.600 ns) + CELL(0.000 ns) = 20.700 ns; Loc. = LC6_A16; Fanout = 5; REG Node = 'ACC\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.600 ns" { FN~27 ACC[15] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns ( 35.27 % ) " "Info: Total cell delay = 7.300 ns ( 35.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.400 ns ( 64.73 % ) " "Info: Total interconnect delay = 13.400 ns ( 64.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns - " "Info: - Micro setup delay of destination is 2.500 ns" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.600 ns - Longest register register " "Info: - Longest register to register delay is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ACC\[15\] 1 REG LC6_A16 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A16; Fanout = 5; REG Node = 'ACC\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { ACC[15] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns rtl~580 2 COMB LC7_A14 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC7_A14; Fanout = 1; COMB Node = 'rtl~580'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.900 ns" { ACC[15] rtl~580 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns rtl~555 3 COMB LC8_A14 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC8_A14; Fanout = 1; COMB Node = 'rtl~555'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "1.500 ns" { rtl~580 rtl~555 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.900 ns rtl~13 4 COMB LC5_A13 1 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC5_A13; Fanout = 1; COMB Node = 'rtl~13'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "4.500 ns" { rtl~555 rtl~13 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 12.300 ns QA~22 5 COMB LC8_A13 2 " "Info: 5: + IC(0.600 ns) + CELL(1.800 ns) = 12.300 ns; Loc. = LC8_A13; Fanout = 2; COMB Node = 'QA~22'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.400 ns" { rtl~13 QA~22 } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 14.600 ns QA 6 REG LC3_A13 2 " "Info: 6: + IC(0.600 ns) + CELL(1.700 ns) = 14.600 ns; Loc. = LC3_A13; Fanout = 2; REG Node = 'QA'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.300 ns" { QA~22 QA } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 61.64 % ) " "Info: Total cell delay = 9.000 ns ( 61.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns ( 38.36 % ) " "Info: Total interconnect delay = 5.600 ns ( 38.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "14.600 ns" { ACC[15] rtl~580 rtl~555 rtl~13 QA~22 QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.600 ns" { ACC[15] rtl~580 rtl~555 rtl~13 QA~22 QA } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns 0.600ns } { 0.000ns 1.700ns 1.500ns 2.300ns 1.800ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] QA } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.700 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.700 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[15] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "14.600 ns" { ACC[15] rtl~580 rtl~555 rtl~13 QA~22 QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.600 ns" { ACC[15] rtl~580 rtl~555 rtl~13 QA~22 QA } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns 0.600ns } { 0.000ns 1.700ns 1.500ns 2.300ns 1.800ns 1.700ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK_4M register N\[1\] register ACC\[1\] -5.3 ns " "Info: Minimum slack time is -5.3 ns for clock \"CLK_4M\" between source register \"N\[1\]\" and destination register \"ACC\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns + Shortest register register " "Info: + Shortest register to register delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns N\[1\] 1 REG LC2_A7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A7; Fanout = 2; REG Node = 'N\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { N[1] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.200 ns) 4.300 ns ACC\[1\] 2 REG LC4_A24 6 " "Info: 2: + IC(3.100 ns) + CELL(1.200 ns) = 4.300 ns; Loc. = LC4_A24; Fanout = 6; REG Node = 'ACC\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "4.300 ns" { N[1] ACC[1] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 27.91 % ) " "Info: Total cell delay = 1.200 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 72.09 % ) " "Info: Total interconnect delay = 3.100 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "4.300 ns" { N[1] ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.300 ns" { N[1] ACC[1] } { 0.000ns 3.100ns } { 0.000ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.600 ns - Smallest register register " "Info: - Smallest register to register requirement is 9.600 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_4M 250.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK_4M\" is 250.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_4M 250.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK_4M\" is 250.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.100 ns + Smallest " "Info: + Smallest clock skew is 9.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M destination 20.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK_4M\" to destination register is 20.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B1 41 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B1; Fanout = 41; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.600 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(1.100 ns) 12.900 ns N\[3\] 3 REG LC3_A6 2 " "Info: 3: + IC(5.400 ns) + CELL(1.100 ns) = 12.900 ns; Loc. = LC3_A6; Fanout = 2; REG Node = 'N\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "6.500 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.300 ns) 18.100 ns FN~27 4 COMB LC4_A17 20 " "Info: 4: + IC(2.900 ns) + CELL(2.300 ns) = 18.100 ns; Loc. = LC4_A17; Fanout = 20; COMB Node = 'FN~27'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.200 ns" { N[3] FN~27 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 20.900 ns ACC\[1\] 5 REG LC4_A24 6 " "Info: 5: + IC(2.800 ns) + CELL(0.000 ns) = 20.900 ns; Loc. = LC4_A24; Fanout = 6; REG Node = 'ACC\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "2.800 ns" { FN~27 ACC[1] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns ( 34.93 % ) " "Info: Total cell delay = 7.300 ns ( 34.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.600 ns ( 65.07 % ) " "Info: Total interconnect delay = 13.600 ns ( 65.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.900 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.900 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 11.800 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_4M\" to source register is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK_4M 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B1 41 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B1; Fanout = 41; REG Node = 'lpm_counter:\\counter:Q\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "3.600 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(0.000 ns) 11.800 ns N\[1\] 3 REG LC2_A7 2 " "Info: 3: + IC(5.400 ns) + CELL(0.000 ns) = 11.800 ns; Loc. = LC2_A7; Fanout = 2; REG Node = 'N\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "5.400 ns" { lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } "NODE_NAME" } "" } } { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 33.05 % ) " "Info: Total cell delay = 3.900 ns ( 33.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 66.95 % ) " "Info: Total interconnect delay = 7.900 ns ( 66.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.900 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.900 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 162 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.900 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.900 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "4.300 ns" { N[1] ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.300 ns" { N[1] ACC[1] } { 0.000ns 3.100ns } { 0.000ns 1.200ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "20.900 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.900 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[3] FN~27 ACC[1] } { 0.000ns 0.000ns 2.500ns 5.400ns 2.900ns 2.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 2.300ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elec_lock" "UNKNOWN" "V1" "F:/备赛资料/VHDL模块/elec_lock/db/elec_lock.quartus_db" { Floorplan "F:/备赛资料/VHDL模块/elec_lock/" "" "11.800 ns" { CLK_4M lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { CLK_4M CLK_4M~out lpm_counter:\counter:Q[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[0] N[1] } { 0.000ns 0.000ns 2.500ns 5.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "CLK_4M 11 " "Warning: Can't achieve minimum setup and hold requirement CLK_4M along 11 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}