all-wcprops

verilog hdl coding DDR sdram control for fpga

K 25
svn:wc:ra_dav:version-url
V 56
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl
END
ddr_top.v
K 25
svn:wc:ra_dav:version-url
V 66
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl/ddr_top.v
END
ddr_par.v
K 25
svn:wc:ra_dav:version-url
V 66
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl/ddr_par.v
END
ddr_sig.v
K 25
svn:wc:ra_dav:version-url
V 66
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl/ddr_sig.v
END
ddr_ctrl.v
K 25
svn:wc:ra_dav:version-url
V 67
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl/ddr_ctrl.v
END
ddr_data.v
K 25
svn:wc:ra_dav:version-url
V 67
/projects/SP1000/!svn/ver/365/main/hw/logic/rtl/ddr_ctrl/ddr_data.v
END