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来自「verilog hdl coding DDR sdram control for」· 代码 · 共 89 行
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89 行
8dir532http://10.1.9.6/projects/SP1000/main/hw/logic/rtl/ddr_ctrlhttp://10.1.9.6/projects/SP10002007-07-02T10:04:18.705009Z365wyusvn:special svn:externals svn:needs-lock62469858-1330-0410-b4df-94defca65d04ddr_top.vfile2007-07-20T09:27:28.000000Z6322a173d3b3c59952e39c9c41cd37632007-07-02T10:04:18.705009Z365wyuddr_par.vfile2007-07-20T09:27:28.000000Z3343288b0f16f097f9239029a32be4c92007-07-02T10:04:18.705009Z365wyuddr_sig.vfile2007-07-20T09:27:28.000000Z6171d9b52c5dfc176c702196c504d0382007-07-02T10:04:18.705009Z365wyuddr_ctrl.vfile2007-07-20T09:27:28.000000Za0ef202ad9fa5ff6450f756a77f898c32007-07-02T10:04:18.705009Z365wyuddr_data.vfile2007-07-20T09:27:28.000000Zf8f32e81e473ac3cee8c7fa15cff54102007-07-02T10:04:18.705009Z365wyu
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