entries

verilog hdl coding DDR sdram control for fpga

8

dir
532
http://10.1.9.6/projects/SP1000/main/hw/logic/rtl/ddr_ctrl
http://10.1.9.6/projects/SP1000



2007-07-02T10:04:18.705009Z
365
wyu


svn:special svn:externals svn:needs-lock











62469858-1330-0410-b4df-94defca65d04

ddr_top.v
file




2007-07-20T09:27:28.000000Z
6322a173d3b3c59952e39c9c41cd3763
2007-07-02T10:04:18.705009Z
365
wyu

ddr_par.v
file




2007-07-20T09:27:28.000000Z
3343288b0f16f097f9239029a32be4c9
2007-07-02T10:04:18.705009Z
365
wyu

ddr_sig.v
file




2007-07-20T09:27:28.000000Z
6171d9b52c5dfc176c702196c504d038
2007-07-02T10:04:18.705009Z
365
wyu

ddr_ctrl.v
file




2007-07-20T09:27:28.000000Z
a0ef202ad9fa5ff6450f756a77f898c3
2007-07-02T10:04:18.705009Z
365
wyu

ddr_data.v
file




2007-07-20T09:27:28.000000Z
f8f32e81e473ac3cee8c7fa15cff5410
2007-07-02T10:04:18.705009Z
365
wyu