testlatch.tan.summary

来自「用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.200 ns
From           : D[7]
To             : JTAGcore:inst4|RD
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.000 ns
From           : JTAGcore:inst4|shiftout:shifter|shifter[0]
To             : ASDI
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.100 ns
From           : CDONE
To             : D[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.100 ns
From           : D[7]
To             : JTAGcore:inst4|RED_LED
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : 25.900 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 70.92 MHz ( period = 14.100 ns )
From           : JTAGcore:inst4|shiftout:shifter|rdy
To             : JTAGcore:inst4|RD
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : 3.900 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : JTAGcore:inst4|SM~167
To             : JTAGcore:inst4|direct
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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