testlatch.map.summary

来自「用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Wed Dec 28 21:28:05 2005
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : testlatch
Top-level Entity Name : testlatch
Family : MAX3000A
Device : EPM3064ATC44-10
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 43
Total pins : 28