testlatch.map.rpt

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机

+----------------+--------+--------+-----------+
; SM.Idle        ; 0      ; 0      ; 0         ;
; SM.ReadString2 ; 1      ; 1      ; 0         ;
; SM.WR_End      ; 1      ; 1      ; 1         ;
; SM.WR_Active   ; 1      ; 0      ; 0         ;
; SM.RD_Active   ; 0      ; 1      ; 0         ;
; SM.ReadString  ; 0      ; 1      ; 1         ;
; SM.Parcer      ; 0      ; 0      ; 1         ;
; SM.ReadString3 ; 1      ; 0      ; 1         ;
+----------------+--------+--------+-----------+


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                         ;
+----------------------------+------------+------+--------------------------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name                        ;
+----------------------------+------------+------+--------------------------------------------+
; |testlatch                 ; 43         ; 28   ; |testlatch                                 ;
;    |JTAGcore:inst4|        ; 42         ; 0    ; |testlatch|JTAGcore:inst4                  ;
;       |shiftout:shifter|   ; 14         ; 0    ; |testlatch|JTAGcore:inst4|shiftout:shifter ;
+----------------------------+------------+------+--------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/RONTEC/POWER/PCI/Altera/testlatch.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; testlatch.bdf                    ; yes             ; D:/RONTEC/POWER/PCI/Altera/testlatch.bdf                            ;
; JtagCore.V                       ; yes             ; D:/RONTEC/POWER/PCI/Altera/JtagCore.V                               ;
; shiftout.v                       ; yes             ; D:/RONTEC/POWER/PCI/Altera/shiftout.v                               ;
; lpm_add_sub.tdf                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; e:/altera/quartus42/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; e:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; e:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal42.inc                    ; yes             ; e:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; addcore.tdf                      ; yes             ; e:/altera/quartus42/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 43                   ;
; Total registers      ; 34                   ;
; I/O pins             ; 28                   ;
; Parallel expanders   ; 4                    ;
; Maximum fan-out node ; N_PWREN              ;
; Maximum fan-out      ; 34                   ;
; Total fan-out        ; 389                  ;
; Average fan-out      ; 5.48                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Tue Dec 13 17:38:10 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off testlatch -c testlatch
Info: Found 1 design units, including 1 entities, in source file testlatch.bdf
    Info: Found entity 1: testlatch
Info: Found 2 design units, including 2 entities, in source file JtagCore.V
    Info: Found entity 1: shiftout
    Info: Found entity 2: JTAGcore
Warning: Verilog HDL assignment warning at JtagCore.V(213): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at JtagCore.V(218): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shiftout.v(48): truncated value with size 32 to match size of target (4)
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|testlatch|JTAGcore:inst4|SM" contains 8 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|testlatch|JTAGcore:inst4|SM"
Info: Encoding result for state machine "|testlatch|JTAGcore:inst4|SM"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "JTAGcore:inst4|SM~127"
        Info: Encoded state bit "JTAGcore:inst4|SM~126"
        Info: Encoded state bit "JTAGcore:inst4|SM~125"
    Info: State "|testlatch|JTAGcore:inst4|SM.Idle" uses code string "000"
    Info: State "|testlatch|JTAGcore:inst4|SM.ReadString2" uses code string "110"
    Info: State "|testlatch|JTAGcore:inst4|SM.WR_End" uses code string "111"
    Info: State "|testlatch|JTAGcore:inst4|SM.WR_Active" uses code string "100"
    Info: State "|testlatch|JTAGcore:inst4|SM.RD_Active" uses code string "010"
    Info: State "|testlatch|JTAGcore:inst4|SM.ReadString" uses code string "011"
    Info: State "|testlatch|JTAGcore:inst4|SM.Parcer" uses code string "001"
    Info: State "|testlatch|JTAGcore:inst4|SM.ReadString3" uses code string "101"
Info: Ignored 7 buffer(s)
    Info: Ignored 7 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 71 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 10 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 43 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue Dec 13 17:38:22 2005
    Info: Elapsed time: 00:00:13