top_fmdm_project.syr

ISE7.1

   Maximum combinational path delay: 13.348ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'uart/u_baud/baud_bclk:Q'
  Clock period: 6.890ns (frequency: 145.127MHz)
  Total number of paths / destination ports: 2301 / 181
-------------------------------------------------------------------------
Delay:               6.890ns (Levels of Logic = 5)
  Source:            uart/u_reciever/rcnt_22 (FF)
  Destination:       uart/u_reciever/state_FFd1 (FF)
  Source Clock:      uart/u_baud/baud_bclk:Q rising
  Destination Clock: uart/u_baud/baud_bclk:Q rising

  Data Path: uart/u_reciever/rcnt_22 to uart/u_reciever/state_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.568   1.010  uart/u_reciever/rcnt_22 (uart/u_reciever/rcnt_22)
     LUT4:I0->O            1   0.439   0.551  uart/u_reciever/Ker638 (CHOICE378)
     LUT4:I2->O            1   0.439   0.726  uart/u_reciever/Ker642 (CHOICE379)
     LUT4:I1->O           10   0.439   0.919  uart/u_reciever/Ker6158 (uart/u_reciever/N6)
     LUT4_D:I2->O          1   0.439   0.551  uart/u_reciever/_n0007 (uart/u_reciever/_n0007)
     LUT4_L:I2->LO         1   0.439   0.000  uart/u_reciever/state_FFd1-In1 (uart/u_reciever/state_FFd1-In)
     FDC:D                     0.370          uart/u_reciever/state_FFd1
    ----------------------------------------
    Total                      6.890ns (3.133ns logic, 3.757ns route)
                                       (45.5% logic, 54.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_select/selected_delay_clk1500:O'
  Clock period: 7.331ns (frequency: 136.406MHz)
  Total number of paths / destination ports: 8269 / 312
-------------------------------------------------------------------------
Delay:               7.331ns (Levels of Logic = 13)
  Source:            pulse_generate/cnt_0 (FF)
  Destination:       pulse_generate/cnt_27 (FF)
  Source Clock:      clk_select/selected_delay_clk1500:O rising
  Destination Clock: clk_select/selected_delay_clk1500:O rising

  Data Path: pulse_generate/cnt_0 to pulse_generate/cnt_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.568   1.056  pulse_generate/cnt_0 (pulse_generate/cnt_0)
     LUT4_L:I0->LO         1   0.439   0.000  pulse_generate/Andlut (pulse_generate/N4)
     MUXCY:S->O            1   0.298   0.000  pulse_generate/Andcy (pulse_generate/And_cyo)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/Andcy_rn_0 (pulse_generate/And_cyo1)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/Andcy_rn_1 (pulse_generate/And_cyo2)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/norcy (pulse_generate/nor_cyo)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/Andcy_rn_2 (pulse_generate/And_cyo3)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/norcy_rn_0 (pulse_generate/nor_cyo1)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/norcy_rn_1 (pulse_generate/nor_cyo2)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/norcy_rn_2 (pulse_generate/nor_cyo3)
     MUXCY:CI->O           1   0.053   0.000  pulse_generate/norcy_rn_3 (pulse_generate/nor_cyo4)
     MUXCY:CI->O          31   0.942   1.125  pulse_generate/GE_stagecy (pulse_generate/_n0006)
     LUT4_D:I3->O         18   0.439   1.231  pulse_generate/_n0010<13>111_SW1 (N1176)
     LUT4_L:I1->LO         1   0.439   0.000  pulse_generate/_n0010<29>111 (pulse_generate/_n0010<29>)
     FDC:D                     0.370          pulse_generate/cnt_29
    ----------------------------------------
    Total                      7.331ns (3.919ns logic, 3.412ns route)
                                       (53.5% logic, 46.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk20mhz'
  Clock period: 6.321ns (frequency: 158.212MHz)
  Total number of paths / destination ports: 1419 / 65
-------------------------------------------------------------------------
Delay:               6.321ns (Levels of Logic = 11)
  Source:            uart/u_baud/cnt_5 (FF)
  Destination:       uart/u_baud/cnt_30 (FF)
  Source Clock:      clk20mhz rising
  Destination Clock: clk20mhz rising

  Data Path: uart/u_baud/cnt_5 to uart/u_baud/cnt_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.568   0.986  uart/u_baud/cnt_5 (uart/u_baud/cnt_5)
     LUT1_L:I0->LO         1   0.439   0.000  uart/u_baud/cnt_5_rt (uart/u_baud/cnt_5_rt)
     MUXCY:S->O            1   0.298   0.000  uart/u_baud/Andcy (uart/u_baud/And_cyo)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy (uart/u_baud/nor_cyo)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_0 (uart/u_baud/nor_cyo1)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_1 (uart/u_baud/nor_cyo2)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_2 (uart/u_baud/nor_cyo3)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_3 (uart/u_baud/nor_cyo4)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_4 (uart/u_baud/nor_cyo5)
     MUXCY:CI->O           1   0.053   0.000  uart/u_baud/norcy_rn_5 (uart/u_baud/nor_cyo6)
     MUXCY:CI->O           2   0.942   0.910  uart/u_baud/GE_stagecy (uart/u_baud/_n0006)
     LUT2:I1->O           32   0.439   1.088  uart/u_baud/_n00041 (uart/u_baud/_n0004)
     FDR:R                     0.280          uart/u_baud/cnt_0
    ----------------------------------------
    Total                      6.321ns (3.337ns logic, 2.984ns route)
                                       (52.8% logic, 47.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_select/selected_delay_clk1500:O'
  Total number of paths / destination ports: 115 / 115
-------------------------------------------------------------------------
Offset:              4.600ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       data_adjust_wide/state_FFd2 (FF)
  Destination Clock: clk_select/selected_delay_clk1500:O rising

  Data Path: reset to data_adjust_wide/state_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            93   0.825   1.246  reset_IBUF (reset_IBUF)
     INV:I->O            311   0.439   1.810  adcnarrow/data_out_toaccumulator_N01_INV_0 (adcnarrow/data_out_toaccumulator_N0)
     FDR:R                     0.280          data_adjust_wide/state_FFd1
    ----------------------------------------
    Total                      4.600ns (1.544ns logic, 3.056ns route)
                                       (33.6% logic, 66.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'data_adjust_log/mux_en:Q'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.914ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       mux_tripple/dataout_mux_7 (LATCH)
  Destination Clock: data_adjust_log/mux_en:Q falling

  Data Path: reset to mux_tripple/dataout_mux_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            93   0.825   1.280  reset_IBUF (reset_IBUF)
     LUT4:I2->O            1   0.439   0.000  mux_tripple/_n0007<2>31 (mux_tripple/_n0002<3>)
     LDCP:D                    0.370          mux_tripple/dataout_mux_3
    ----------------------------------------
    Total                      2.914ns (1.634ns logic, 1.280ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk20mhz'
  Total number of paths / destination ports: 33 / 33
-------------------------------------------------------------------------
Offset:              4.162ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       uart/u_baud/cnt_30 (FF)
  Destination Clock: clk20mhz rising

  Data Path: reset to uart/u_baud/cnt_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            93   0.825   1.531  reset_IBUF (reset_IBUF)
     LUT2:I0->O           32   0.439   1.088  uart/u_baud/_n00041 (uart/u_baud/_n0004)
     FDR:R                     0.280          uart/u_baud/cnt_0
    ----------------------------------------
    Total                      4.162ns (1.544ns logic, 2.618ns route)
                                       (37.1% logic, 62.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'uart/u_baud/baud_bclk:Q'
  Total number of paths / destination ports: 50 / 46
-------------------------------------------------------------------------
Offset:              4.854ns (Levels of Logic = 4)
  Source:            max3232_rec_fpga (PAD)
  Destination:       uart/u_reciever/state_FFd2 (FF)
  Destination Clock: uart/u_baud/baud_bclk:Q rising

  Data Path: max3232_rec_fpga to uart/u_reciever/state_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            13   0.825   1.239  max3232_rec_fpga_IBUF (max3232_rec_fpga_IBUF)
     LUT3:I0->O            1   0.439   0.551  uart/u_reciever/state_FFd2-In17 (CHOICE341)
     LUT3:I2->O            1   0.439   0.551  uart/u_reciever/state_FFd2-In23 (CHOICE343)
     LUT4_L:I2->LO         1   0.439   0.000  uart/u_reciever/state_FFd2-In29 (uart/u_reciever/state_FFd2-In)
     FDC:D                     0.370          uart/u_reciever/state_FFd2
    ----------------------------------------
    Total                      4.854ns (2.512ns logic, 2.342ns route)
                                       (51.7% logic, 48.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uart/u_baud/baud_bclk:Q'
  Total number of paths / destination ports: 83 / 13
-------------------------------------------------------------------------
Offset:              13.559ns (Levels of Logic = 7)
  Source:            clk_select/command_1 (FF)
  Destination:       adc2_clk (PAD)
  Source Clock:      uart/u_baud/baud_bclk:Q rising

  Data Path: clk_select/command_1 to adc2_clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            11   0.568   1.194  clk_select/command_1 (clk_select/command_1)
     LUT4:I0->O            1   0.439   0.802  clk_select/selected_delay_clk1111 (CHOICE255)
     LUT4:I0->O            1   0.439   0.802  clk_select/selected_delay_clk1123 (CHOICE257)
     LUT4:I0->O            1   0.439   0.726  clk_select/selected_delay_clk1147 (CHOICE259)
     LUT4:I1->O            1   0.439   0.000  clk_select/selected_delay_clk1500_G (N1274)
     MUXF5:I1->O           1   0.436   0.517  clk_select/selected_delay_clk1500 (selected_clk)
     BUFG:I->O           310   0.589   1.808  buf_g (adc1_clk_OBUF)
     OBUF:I->O                 4.361          adc2_clk_OBUF (adc2_clk)
    ----------------------------------------
    Total                     13.559ns (7.710ns logic, 5.849ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_select/selected_delay_clk1500:O'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              5.654ns (Levels of Logic = 1)
  Source:            pulse_generate/narrow_wide_pulse (FF)
  Destination:       fmdm_select (PAD)
  Source Clock:      clk_select/selected_delay_clk1500:O rising

  Data Path: pulse_generate/narrow_wide_pulse to fmdm_select
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              3   0.568   0.725  pulse_generate/narrow_wide_pulse (pulse_generate/narrow_wide_pulse)
     OBUF:I->O                 4.361          fmdm_select_OBUF (fmdm_select)
    ----------------------------------------
    Total                      5.654ns (4.929ns logic, 0.725ns route)
                                       (87.2% logic, 12.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 52 / 2
-------------------------------------------------------------------------
Delay:               13.348ns (Levels of Logic = 8)
  Source:            delay_in<16> (PAD)
  Destination:       adc2_clk (PAD)

  Data Path: delay_in<16> to adc2_clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.825   0.726  delay_in_16_IBUF (delay_in_16_IBUF)
     LUT4:I1->O            1   0.439   0.802  clk_select/selected_delay_clk1111 (CHOICE255)
     LUT4:I0->O            1   0.439   0.802  clk_select/selected_delay_clk1123 (CHOICE257)
     LUT4:I0->O            1   0.439   0.726  clk_select/selected_delay_clk1147 (CHOICE259)
     LUT4:I1->O            1   0.439   0.000  clk_select/selected_delay_clk1500_G (N1274)
     MUXF5:I1->O           1   0.436   0.517  clk_select/selected_delay_clk1500 (selected_clk)
     BUFG:I->O           310   0.589   1.808  buf_g (adc1_clk_OBUF)
     OBUF:I->O                 4.361          adc2_clk_OBUF (adc2_clk)
    ----------------------------------------
    Total                     13.348ns (7.967ns logic, 5.381ns route)
                                       (59.7% logic, 40.3% route)

=========================================================================
CPU : 22.17 / 22.67 s | Elapsed : 22.00 / 22.00 s
 
--> 

Total memory usage is 113616 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   64 (   0 filtered)
Number of infos    :    2 (   0 filtered)