top_fmdm_project.syr
来自「ISE7.1」· SYR 代码 · 共 1,049 行 · 第 1/4 页
SYR
1,049 行
Unit <baud> synthesized.Synthesizing Unit <narrow_wide_pulse_generate>. Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd". Found finite state machine <FSM_2> for signal <state>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 3 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | reset (negative) | | Reset type | asynchronous | | Reset State | log | | Power Up State | log | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <narrow_wide_pulse>. Found 32-bit comparator greatequal for signal <$n0004> created at line 49. Found 32-bit comparator greater for signal <$n0005> created at line 58. Found 32-bit comparator greatequal for signal <$n0006> created at line 67. Found 32-bit adder for signal <$n0012> created at line 47. Found 32-bit register for signal <cnt>. Summary: inferred 1 Finite State Machine(s). inferred 33 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 3 Comparator(s).Unit <narrow_wide_pulse_generate> synthesized.Synthesizing Unit <readfifo_RS232>. Related source file is "F:/vhdlproject/vhdl0716/readfifo_rs232.vhd". Register <trans_com> equivalent to <fifo_enable> has been removed Found finite state machine <FSM_3> for signal <state>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 2 | | Outputs | 1 | | Clock | rs232_clk_read (rising_edge) | | Reset | reset (negative) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <fifo_enable>. Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s).Unit <readfifo_RS232> synthesized.Synthesizing Unit <mux_log_wide_narrow>. Related source file is "F:/vhdlproject/vhdl0716/mux_log_wide_narrow.vhd".WARNING:Xst:646 - Signal <command<4:0>> is assigned but never used.WARNING:Xst:737 - Found 8-bit latch for signal <dataout_mux>. Found 8-bit 4-to-1 multiplexer for signal <$n0002>. Found 8-bit 4-to-1 multiplexer for signal <$n0005>. Found 8-bit register for signal <command>. Summary: inferred 8 D-type flip-flop(s). inferred 16 Multiplexer(s).Unit <mux_log_wide_narrow> synthesized.Synthesizing Unit <dataformat_adjust_widefreq>. Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_widefreq.vhd".WARNING:Xst:647 - Input <data_in<5:0>> is never used. Found finite state machine <FSM_4> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal <dataout_widefreq>. Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_widefreq> synthesized.Synthesizing Unit <dataformat_adjust_narrowfreq>. Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_narrowfreq.vhd".WARNING:Xst:647 - Input <data_in<5:0>> is never used. Found finite state machine <FSM_5> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <dataout_narrowfreq>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_narrowfreq> synthesized.Synthesizing Unit <dataformat_adjust_log>. Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_log.vhd".WARNING:Xst:647 - Input <data_in<5:0>> is never used. Found finite state machine <FSM_6> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <dataout_log>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_log> synthesized.Synthesizing Unit <accumulator_ctr_dataadjust>. Related source file is "F:/vhdlproject/vhdl0716/accumulator_ctr_dataadjust.vhd". Found 1-bit register for signal <accumulator_clr_clk>. Found 1-bit register for signal <accumulator_send_clk>. Found 10-bit comparator greatequal for signal <$n0005> created at line 60. Found 10-bit comparator greatequal for signal <$n0007> created at line 47. Found 10-bit up counter for signal <accumulator_clr_clk_counter>. Found 10-bit up counter for signal <accumulator_send_clk_counter>. Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s).Unit <accumulator_ctr_dataadjust> synthesized.Synthesizing Unit <add_accumulator>. Related source file is "F:/vhdlproject/vhdl0716/add_accumulator.vhd". Found 22-bit register for signal <Q>. Found 22-bit adder for signal <$n0002> created at line 55. Found 22-bit register for signal <q_buf>. Summary: inferred 44 D-type flip-flop(s). inferred 1 Adder/Subtractor(s).Unit <add_accumulator> synthesized.Synthesizing Unit <adc_control>. Related source file is "F:/vhdlproject/vhdl0716/adc_control.vhd". Found 12-bit register for signal <data_out_toaccumulator>. Found 12-bit subtractor for signal <$n0000> created at line 65. Summary: inferred 12 D-type flip-flop(s). inferred 1 Adder/Subtractor(s).Unit <adc_control> synthesized.Synthesizing Unit <select_clk>. Related source file is "F:/vhdlproject/vhdl0716/select_clk.vhd".WARNING:Xst:646 - Signal <command<7:5>> is assigned but never used. Found 8-bit register for signal <command>. Summary: inferred 8 D-type flip-flop(s).Unit <select_clk> synthesized.Synthesizing Unit <top_uart>. Related source file is "F:/vhdlproject/vhdl0716/top_uart.vhd".Unit <top_uart> synthesized.Synthesizing Unit <top_fmdm_project>. Related source file is "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd".Unit <top_fmdm_project> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_6> for best encoding.Optimizing FSM <FSM_6> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_5> for best encoding.Optimizing FSM <FSM_5> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_4> for best encoding.Optimizing FSM <FSM_4> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_3> for best encoding.Optimizing FSM <FSM_3> on signal <state[1:2]> with sequential encoding.---------------------------------- State | Encoding---------------------------------- idle | 00 rd_en_trcom_generate | 01 cmd_cancel | 10----------------------------------Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <FSM_2> on signal <state[1:2]> with sequential encoding.-------------------- State | Encoding-------------------- log | 00 narrow | 01 wide | 10--------------------Analyzing FSM <FSM_1> for best encoding.⌨️ 快捷键说明
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