top_fmdm_project.syr

ISE7.1

Optimizing FSM <FSM_1> on signal <state[1:3]> with sequential encoding.
----------------------
 State    | Encoding
----------------------
 r_start  | 000
 r_center | 001
 r_wait   | 010
 r_sample | 100
 r_stop   | 011
----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:5]> with speed1 encoding.
---------------------
 State   | Encoding
---------------------
 x_idle  | 10000
 x_start | 01000
 x_wait  | 00100
 x_shift | 00001
 x_stop  | 00010
---------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 7
# Adders/Subtractors               : 11
 12-bit subtractor                 : 3
 22-bit adder                      : 3
 32-bit adder                      : 3
 4-bit adder                       : 1
 5-bit adder                       : 1
# Counters                         : 3
 10-bit up counter                 : 2
 32-bit up counter                 : 1
# Registers                        : 63
 1-bit register                    : 37
 12-bit register                   : 3
 22-bit register                   : 6
 32-bit register                   : 3
 4-bit register                    : 1
 5-bit register                    : 1
 8-bit register                    : 12
# Latches                          : 1
 8-bit latch                       : 1
# Comparators                      : 10
 10-bit comparator greatequal      : 2
 32-bit comparator greatequal      : 3
 32-bit comparator greater         : 1
 32-bit comparator less            : 1
 4-bit comparator greatequal       : 1
 5-bit comparator greatequal       : 2
# Multiplexers                     : 2
 8-bit 4-to-1 multiplexer          : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading module "fifo_rs232.ngo" ( "fifo_rs232.ngo" unchanged since last run )...
Loading core <fifo_rs232> for timing and area information for instance <fifo>.
WARNING:Xst:1291 - FF/Latch <command_7> is unconnected in block <select_clk>.
WARNING:Xst:1291 - FF/Latch <command_5> is unconnected in block <select_clk>.
WARNING:Xst:1291 - FF/Latch <command_6> is unconnected in block <select_clk>.
WARNING:Xst:1291 - FF/Latch <command_0> is unconnected in block <mux_log_wide_narrow>.
WARNING:Xst:1291 - FF/Latch <command_1> is unconnected in block <mux_log_wide_narrow>.
WARNING:Xst:1291 - FF/Latch <command_2> is unconnected in block <mux_log_wide_narrow>.
WARNING:Xst:1291 - FF/Latch <command_3> is unconnected in block <mux_log_wide_narrow>.
WARNING:Xst:1291 - FF/Latch <command_4> is unconnected in block <mux_log_wide_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_log>.
WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_wide>.
WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_narrow>.
WARNING:Xst:1291 - FF/Latch <mux_en> is unconnected in block <data_adjust_narrow>.
WARNING:Xst:1291 - FF/Latch <mux_en> is unconnected in block <data_adjust_wide>.
WARNING:Xst:1988 - Unit <baud>: instances <Mcompar__n0006>, <Mcompar__n0007> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_5> are dual, second instance is removed

Optimizing unit <top_fmdm_project> ...

Optimizing unit <dataformat_adjust_widefreq> ...

Optimizing unit <readfifo_RS232> ...

Optimizing unit <narrow_wide_pulse_generate> ...

Optimizing unit <accumulator_ctr_dataadjust> ...

Optimizing unit <mux_log_wide_narrow> ...

Optimizing unit <baud> ...

Optimizing unit <reciever> ...

Optimizing unit <dataformat_adjust_narrowfreq> ...

Optimizing unit <transfer> ...
WARNING:Xst:1293 - FF/Latch  <xcnt16_4> has a constant value of 0 in block <transfer>.

Optimizing unit <select_clk> ...

Optimizing unit <dataformat_adjust_log> ...

Optimizing unit <add_accumulator> ...
Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <data_adjust_wide/mux_en> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <data_adjust_narrow/mux_en> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_0> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_1> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_2> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_3> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_4> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_5> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_0> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_1> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_2> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_3> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_4> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_5> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_0> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_1> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_2> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_3> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_4> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_5> is unconnected in block <top_fmdm_project>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_fmdm_project, actual ratio is 14.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_fmdm_project.ngr
Top Level Output File Name         : top_fmdm_project
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 74

Macro Statistics :
# Registers                        : 48
#      1-bit register              : 19
#      12-bit register             : 3
#      22-bit register             : 6
#      32-bit register             : 6
#      4-bit register              : 1
#      5-bit register              : 1
#      8-bit register              : 12
# Multiplexers                     : 2
#      8-bit 4-to-1 multiplexer    : 2
# Adders/Subtractors               : 9
#      22-bit adder                : 3
#      32-bit adder                : 6
# Comparators                      : 10
#      10-bit comparator greatequal: 2
#      32-bit comparator greatequal: 3
#      32-bit comparator greater   : 1
#      32-bit comparator less      : 1
#      4-bit comparator greatequal : 1
#      5-bit comparator greatequal : 2

Cell Usage :
# BELS                             : 1270
#      GND                         : 2
#      INV                         : 17
#      LUT1                        : 30
#      LUT1_L                      : 144
#      LUT2                        : 25
#      LUT2_L                      : 108
#      LUT3                        : 68
#      LUT3_D                      : 5
#      LUT3_L                      : 12
#      LUT4                        : 169
#      LUT4_D                      : 8
#      LUT4_L                      : 162
#      MUXCY                       : 261
#      MUXCY_D                     : 2
#      MUXCY_L                     : 4
#      MUXF5                       : 32
#      VCC                         : 2
#      XORCY                       : 219
# FlipFlops/Latches                : 508
#      FDC                         : 286
#      FDCE                        : 59
#      FDE                         : 64
#      FDP                         : 10
#      FDPE                        : 11
#      FDR                         : 69
#      FDRS                        : 1
#      LDCP                        : 8
# RAMS                             : 1
#      RAMB16_S9_S9                : 1
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 73
#      IBUF                        : 59
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v500fg456-4 

 Number of Slices:                     444  out of   3072    14%  
 Number of Slice Flip Flops:           508  out of   6144     8%  
 Number of 4 input LUTs:               731  out of   6144    11%  
 Number of bonded IOBs:                 74  out of    264    28%  
 Number of BRAMs:                        1  out of     32     3%  
 Number of GCLKs:                        3  out of     16    18%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------+-----------------------------+-------+
Clock Signal                                     | Clock buffer(FF name)       | Load  |
-------------------------------------------------+-----------------------------+-------+
uart/u_baud/baud_bclk:Q                          | BUFG                        | 149   |
selected_clk(clk_select/selected_delay_clk1500:O)| BUFG(*)(acumulator_log/Q_19)| 318   |
fifo/GND:G                                       | NONE                        | 2     |
data_adjust_log/mux_en:Q                         | NONE                        | 8     |
clk20mhz                                         | BUFGP                       | 33    |
-------------------------------------------------+-----------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.331ns (Maximum Frequency: 136.406MHz)
   Minimum input arrival time before clock: 4.854ns
   Maximum output required time after clock: 13.559ns