top_fmdm_project.syr

ISE7.1

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top_fmdm_project.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top_fmdm_project.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top_fmdm_project"
Output Format                      : NGC
Target Device                      : xc2v500-4-fg456

---- Source Options
Top Module Name                    : top_fmdm_project
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top_fmdm_project.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "F:/vhdlproject/vhdl0716/fifo_rs232.vhd. Ignore this file from project file "top_fmdm_project_vhdl.prj".
Compiling vhdl file "F:/vhdlproject/vhdl0716/baud.vhd" in Library work.
Architecture behavioral of Entity baud is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/reciever.vhd" in Library work.
Architecture behavioral of Entity reciever is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/transfer.vhd" in Library work.
Architecture behavioral of Entity transfer is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/top_uart.vhd" in Library work.
Architecture behavioral of Entity top_uart is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/select_clk.vhd" in Library work.
Architecture behavioral of Entity select_clk is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/adc_control.vhd" in Library work.
Architecture behavioral of Entity adc_control is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/add_accumulator.vhd" in Library work.
Architecture behavioral of Entity add_accumulator is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/accumulator_ctr_dataadjust.vhd" in Library work.
Architecture behavioral of Entity accumulator_ctr_dataadjust is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_log.vhd" in Library work.
Architecture behavioral of Entity dataformat_adjust_log is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_narrowfreq.vhd" in Library work.
Architecture behavioral of Entity dataformat_adjust_narrowfreq is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_widefreq.vhd" in Library work.
Architecture behavioral of Entity dataformat_adjust_widefreq is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/mux_log_wide_narrow.vhd" in Library work.
Architecture behavioral of Entity mux_log_wide_narrow is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/readfifo_rs232.vhd" in Library work.
Architecture behavioral of Entity readfifo_rs232 is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
Architecture behavioral of Entity narrow_wide_pulse_generate is up to date.
Compiling vhdl file "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" in Library work.
Architecture behavioral of Entity top_fmdm_project is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_fmdm_project> (Architecture <behavioral>).
WARNING:Xst:766 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 221: Generating a Black Box for component <BUFG>.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 268: Unconnected output port 'mux_en' of component 'dataformat_adjust_narrowfreq'.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 275: Unconnected output port 'mux_en' of component 'dataformat_adjust_widefreq'.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 291: Unconnected output port 'full' of component 'fifo_rs232'.
WARNING:Xst:766 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 291: Generating a Black Box for component <fifo_rs232>.
Entity <top_fmdm_project> analyzed. Unit <top_fmdm_project> generated.

Analyzing Entity <top_uart> (Architecture <behavioral>).
WARNING:Xst:1542 - "F:/vhdlproject/vhdl0716/top_uart.vhd" line 78: No default binding for component: <reciever>. Generic <framlenr> is not on the component.
WARNING:Xst:1542 - "F:/vhdlproject/vhdl0716/top_uart.vhd" line 85: No default binding for component: <transfer>. Generic <framlent> is not on the component.
Entity <top_uart> analyzed. Unit <top_uart> generated.

Analyzing Entity <baud> (Architecture <behavioral>).
Entity <baud> analyzed. Unit <baud> generated.

Analyzing Entity <reciever> (Architecture <behavioral>).
Entity <reciever> analyzed. Unit <reciever> generated.

Analyzing Entity <transfer> (Architecture <behavioral>).
Entity <transfer> analyzed. Unit <transfer> generated.

Analyzing Entity <select_clk> (Architecture <behavioral>).
Entity <select_clk> analyzed. Unit <select_clk> generated.

Analyzing Entity <adc_control> (Architecture <behavioral>).
Entity <adc_control> analyzed. Unit <adc_control> generated.

Analyzing Entity <add_accumulator> (Architecture <behavioral>).
Entity <add_accumulator> analyzed. Unit <add_accumulator> generated.

Analyzing Entity <accumulator_ctr_dataadjust> (Architecture <behavioral>).
Entity <accumulator_ctr_dataadjust> analyzed. Unit <accumulator_ctr_dataadjust> generated.

Analyzing Entity <dataformat_adjust_log> (Architecture <behavioral>).
Entity <dataformat_adjust_log> analyzed. Unit <dataformat_adjust_log> generated.

Analyzing Entity <dataformat_adjust_narrowfreq> (Architecture <behavioral>).
Entity <dataformat_adjust_narrowfreq> analyzed. Unit <dataformat_adjust_narrowfreq> generated.

Analyzing Entity <dataformat_adjust_widefreq> (Architecture <behavioral>).
Entity <dataformat_adjust_widefreq> analyzed. Unit <dataformat_adjust_widefreq> generated.

Analyzing Entity <mux_log_wide_narrow> (Architecture <behavioral>).
Entity <mux_log_wide_narrow> analyzed. Unit <mux_log_wide_narrow> generated.

Analyzing Entity <readfifo_RS232> (Architecture <behavioral>).
Entity <readfifo_RS232> analyzed. Unit <readfifo_RS232> generated.

Analyzing Entity <narrow_wide_pulse_generate> (Architecture <behavioral>).
Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <transfer>.
    Related source file is "F:/vhdlproject/vhdl0716/transfer.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkt (rising_edge)                            |
    | Reset              | resett (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | x_idle                                         |
    | Power Up State     | x_idle                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <txd_done>.
    Found 5-bit comparator greatequal for signal <$n0006> created at line 68.
    Found 5-bit comparator greatequal for signal <$n0007> created at line 78.
    Found 5-bit adder for signal <$n0018> created at line 58.
    Found 32-bit adder for signal <$n0019> created at line 92.
    Found 1-bit register for signal <txds>.
    Found 32-bit register for signal <xbitcnt>.
    Found 5-bit register for signal <xcnt16>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <transfer> synthesized.


Synthesizing Unit <reciever>.
    Related source file is "F:/vhdlproject/vhdl0716/reciever.vhd".
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkr (rising_edge)                            |
    | Reset              | resetr (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | r_start                                        |
    | Power Up State     | r_start                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <rbuf>.
    Found 1-bit register for signal <r_ready>.
    Found 4-bit comparator greatequal for signal <$n0006> created at line 63.
    Found 4-bit adder for signal <$n0024> created at line 41.
    Found 32-bit adder for signal <$n0025> created at line 76.
    Found 4-bit register for signal <count>.
    Found 8-bit register for signal <rbufs>.
    Found 32-bit register for signal <rcnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  53 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <reciever> synthesized.


Synthesizing Unit <baud>.
    Related source file is "F:/vhdlproject/vhdl0716/baud.vhd".
    Found 1-bit register for signal <baud_bclk>.
    Found 32-bit comparator greatequal for signal <$n0006> created at line 45.
    Found 32-bit comparator less for signal <$n0007> created at line 45.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).