compute_pipe_ch31.v

来自「利用2個加法器及2個乘法器加上平行化處理來實現」· Verilog 代码 · 共 16 行

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *********************                                                                                                                      
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                                      
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                                      
//************************************ Rev : V1.2	             *******************************************                                                                                                                      
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                                      
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                                      
//**************************************************************************************************************                                                                                                                      
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                                      
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                                      
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                                      
//**************************************************************************************************************                                                                                                                      

`timescale 1ns/1ns                                                                      

module COMPUTE_PIPE_CH31 (CLK, RST, REQ, IN_TAG, X_DIN, Y_DIN, Z_DIN, A, B, C, TAGOUT, DXOUT, DYOUT, DZOUT);   
//input signal  (块