📄 compute_pipe1.v
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//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************
//************************************ Copyright by @CDJ Co,.LTD *******************************************
//************************************ Dpt : ASIC R&D Dpt. *******************************************
//************************************ Rev : V1.2 *******************************************
//************************************ Author : Kevin Chiang *******************************************
//************************************ Modify : 2004/12/19 *******************************************
//**************************************************************************************************************
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********
//**************************************************************************************************************
// input => R-G-B-
// MAMAMA
// A B C =>output
//***********************************************************************************
`timescale 1ns/1ns
module COMPUTE_PIPE1 (CLK, RST, REQ, IN_TAG, A, B,DIN, TAGOUT, TAGVLD, DOUT);
//input signal
input RST,CLK;
input [7:0] A,B;
input [2:0] IN_TAG;
input [7:0] DIN;
input REQ;
//output signal
output TAGOUT;
output TAGVLD;
output [7:0] DOUT;
wire [2:0] TAGOUT;
wire TAGVLD;
wire [7:0] DOUT;
////////////////////////////////////////////////////////////////
// W_DIN,Y_DIN
////////////////////////////////////////////////////////////////
reg vailda,vaildb,vaildc;
reg [7:0] W_DIN,X_DIN;
always @(IN_TAG)begin
if (~RST)
{vailda,vaildb,vaildc} <=3'b000;
else
case (IN_TAG)
IN_TAG[2]: vailda <= ~IN_TAG[2];
IN_TAG[1]: vaildb <= ~IN_TAG[1];
IN_TAG[0]: vaildc <= ~IN_TAG[0];
endcase
end
always @(posedge CLK)begin
case (IN_TAG)
(IN_TAG[2] & vailda): W_DIN <= DIN;
(IN_TAG[1] & vaildb): W_DIN <= DIN;
(IN_TAG[0] & vaildc): W_DIN <= DIN;
default: W_DIN <= W_DIN;
endcase
end
always @(posedge CLK)begin
case (IN_TAG)
(IN_TAG[2] & ~vailda): X_DIN <= DIN;
(IN_TAG[1] & ~vaildb): X_DIN <= DIN;
(IN_TAG[0] & ~vaildc): X_DIN <= DIN;
default: X_DIN <= X_DIN;
endcase
end
/////////////////////////////////////////////////////////////////////////////
// parameter of the registers
/////////////////////////////////////////////////////////////////////////////
reg [7:0] multiplicator_A,faciend_A;
reg [7:0] multiplicator_B,faciend_B;
reg [15:0] addend_A,summand_A;
reg [15:0] addend_B,summand_B;
wire [15:0] MULER_A,MULER_B;
wire [16:0] ADDER_A;
wire [15:0] MULER_C,MULER_D;
wire [16:0] ADDER_B;
wire [16:0] TADD_A;
wire [16:0] TADD_B;
reg [16:0] TRA;
reg [16:0] TRB;
//reg [7:0] A_DIN,B_DIN;
//////////////////////////////////////////////////////////////////////////////
reg [1:0] state,state_next;
parameter [1:0] MUL_A = 2'b00,
ADD_A = 2'b01,
MUL_B = 2'b10,
ADD_B = 2'b11;
always @(state or REQ ) begin
case (state)
MUL_A: begin
if (~REQ)
state_next = ADD_A;
else
state_next = MUL_A;
multiplicator_A <= W_DIN;
faciend_A <= A;
multiplicator_B <= TADD_B;
faciend_B <= B;
end
ADD_A: begin
state_next = MUL_B;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
MUL_B: begin
state_next = ADD_B;
multiplicator_A <= TADD_A;
faciend_A <= B;
multiplicator_B <= X_DIN;
faciend_B <= A;
end
ADD_B: begin
state_next = MUL_A;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
default: state_next = MUL_A;
endcase
end
always @(posedge CLK or negedge RST)begin
if (~RST)
state = MUL_A;
else
state = state_next;
end
//****************************MUL * 2 ********************************
//****************************ADD * 2 ********************************
assign MULER_A = multiplicator_A * faciend_A;//A
assign MULER_B = multiplicator_A * faciend_A;//B
assign MULER_C = multiplicator_B * faciend_B;//C
assign MULER_D = multiplicator_B * faciend_B;//D
assign TADD_A = addend_A + summand_A;
assign TADD_B = addend_B + summand_B;
assign ADDER_A = TADD_A + TRA;
assign ADDER_B = TADD_B + TRB;
/////////////////////////////////////////////////////////////////
// TEMP_RDA,TEMP_RDB;
/////////////////////////////////////////////////////////////////
reg [16:0] TEMP_RDA,TEMP_RDB;
always @(state or ADDER_B)begin
if (state == ADD_B)
begin
TEMP_RDA <= ADDER_A;
end
else
begin
TEMP_RDA <= TEMP_RDB;
end
end
always @(state or ADDER_B)begin
if (state == ADD_A)
begin
TEMP_RDB <= ADDER_B;
end
else
begin
TEMP_RDB <= TEMP_RDB;
end
end
/////////////////////////////////////////////////////////////////
// TADD_A,TADD_B;
/////////////////////////////////////////////////////////////////
always @(state or TADD_A)begin
if (state == ADD_A)begin
TRA <= TADD_A;
end
else begin
TRA <= TRA;
end
end
always @(state or TADD_B)begin
if (state == ADD_B)begin
TRB <= TADD_B;
end
else begin
TRB <= TRB;
end
end
/////////////////////////////////////////////////////////////////
// wotag,xotag;
/////////////////////////////////////////////////////////////////
reg tagout;
always @(state)begin
if ((state == ADD_B) ||(state == ADD_A))begin
tagout = 1'b1;
end
else
begin
tagout = 1'b0;
end
end
reg [16:0] D_OUT;
always @(state)begin
case (state)
state == ADD_A : D_OUT = ADDER_A;
state == ADD_B : D_OUT = ADDER_B;
default : D_OUT = DOUT;
endcase
end
reg [2:0] TAG_OUT;
always @(posedge CLK or negedge RST) begin
if(~RST)
TAG_OUT <= 3'b001;
else
if(state == ADD_B)
TAG_OUT <= IN_TAG;
else
TAG_OUT <= TAG_OUT;
end
assign TAGVLD = tagout;
assign TAGOUT = TAG_OUT;
assign DOUT = D_OUT;
endmodule
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