📄 compute_pipe_ch3.v
字号:
//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************
//************************************ Copyright by @CDJ Co,.LTD *******************************************
//************************************ Dpt : ASIC R&D Dpt. *******************************************
//************************************ Rev : V1.2 *******************************************
//************************************ Author : Kevin Chiang *******************************************
//************************************ Modify : 2004/12/19 *******************************************
//**************************************************************************************************************
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********
//**************************************************************************************************************
// input => R-G-B-
// MAMAMA
// A B C =>output
//***********************************************************************************
`timescale 1ns/1ns
module COMPUTE_PIPE_CH3 (CLK, RST, REQ, IN_TAG, X_DIN, Y_DIN, Z_DIN, A, B, C, TAGOUT, DXOUT, DYOUT, DZOUT);
//input signal
input RST,CLK;
input [15:0] A,B,C;
input [2:0] IN_TAG;
input [15:0] X_DIN;
input [15:0] Y_DIN;
input [15:0] Z_DIN;
input REQ;
//output signal
output [2:0] TAGOUT;
output [32:0] DXOUT;
output [32:0] DYOUT;
output [32:0] DZOUT;
wire [2:0] TAGOUT;
wire [32:0] DXOUT;
wire [32:0] DYOUT;
wire [32:0] DZOUT;
/*
//*************************************************************
//(XDIN * A)+ (XDIN * A) * B + (XDIN * C)
//(YDIN * A)+ (YDIN * A) * B + (YDIN * C)
//(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)
//*************************************************************
////////////////////////////////////////////////////////////////
// Y_DIN,X_DIN,Z_DIN
////////////////////////////////////////////////////////////////
reg [15:0] X_DIN,Y_DIN,Z_DIN;
always @(posedge CLK or negedge RST)begin
if (~RST)
begin
X_DIN <= 16'h0;
Y_DIN <= 16'h0;
Z_DIN <= 16'h0;
end
else begin
case (1'b1)
IN_TAG[2] : Z_DIN <= DIN;
IN_TAG[1] : Y_DIN <= DIN;
IN_TAG[0] : X_DIN <= DIN;
endcase
end
end
*/
/////////////////////////////////////////////////////////////////////////////
// parameter of the registers
/////////////////////////////////////////////////////////////////////////////
reg [15:0] multiplicator_A,faciend_A;
reg [15:0] multiplicator_B,faciend_B;
reg [15:0] multiplicator_C,faciend_C;
reg [15:0] addend_A,summand_A;
reg [15:0] addend_B,summand_B;
reg [15:0] addend_C,summand_C;
wire [31:0] MULER_A,MULER_B;
wire [31:0] MULER_C,MULER_D;
wire [31:0] MULER_E,MULER_F;
wire [32:0] ADDER_A;
wire [32:0] ADDER_B;
wire [32:0] ADDER_C;
wire [31:0] TADD_A;
wire [31:0] TADD_B;
wire [31:0] TADD_C;
reg [31:0] TRDA;
reg [31:0] TRDB;
reg [31:0] TRDC;
reg [24:0] TEMP_RDA,TEMP_RDB,TEMP_RDC;
//////////////////////////////////////////////////////////////////////////////
reg [2:0] state,state_next;
parameter [2:0] MUL_A = 3'b000,
ADD_A = 3'b001,
MUL_B = 3'b010,
ADD_B = 3'b011,
MUL_C = 3'b100,
ADD_C = 3'b101;
always @(state or REQ ) begin
case (state)
MUL_A: begin
if (~REQ)
state_next = ADD_A;
else
state_next = MUL_A;
multiplicator_A <= X_DIN;
faciend_A <= A;
multiplicator_B <= Y_DIN;
faciend_B <= C;
multiplicator_C <= TEMP_RDC;
faciend_C <= B;
end
ADD_A: begin
state_next = MUL_B;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
addend_C <= MULER_E;
summand_C <= MULER_F;
end
MUL_B: begin
state_next = ADD_B;
multiplicator_A <= TEMP_RDA;
faciend_A <= B;
multiplicator_B <= Y_DIN;
faciend_B <= A;
multiplicator_C <= Z_DIN;
faciend_C <= C;
end
ADD_B: begin
state_next = MUL_C;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
addend_C <= MULER_E;
summand_C <= MULER_F;
end
MUL_C: begin
state_next = ADD_C;
multiplicator_A <= X_DIN;
faciend_A <= C;
multiplicator_B <= TEMP_RDB;
faciend_B <= B;
multiplicator_C <= Z_DIN;
faciend_C <= A;
end
ADD_C: begin
state_next = MUL_A;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
addend_C <= MULER_E;
summand_C <= MULER_F;
end
default: state_next = MUL_A;
endcase
end
always @(posedge CLK or negedge RST)begin
if (~RST)
state = MUL_A;
else
state = state_next;
end
//****************************MUL * 2 ********************************
//****************************ADD * 2 ********************************
assign MULER_A = multiplicator_A[31:16] * faciend_A;//A
assign MULER_B = multiplicator_A[15:0] * faciend_A;//B
assign MULER_C = multiplicator_B[31:16] * faciend_B;//C
assign MULER_D = multiplicator_B[15:0] * faciend_B;//D
assign MULER_E = multiplicator_C[31:16] * faciend_C;//C
assign MULER_F = multiplicator_C[15:0] * faciend_C;//D
assign TADD_A = {addend_A,16'h0} + summand_A;
assign TADD_B = {addend_B,16'h0} + summand_B;
assign TADD_C = {addend_C,16'h0} + summand_C;
assign ADDER_A = TADD_A + TEMP_RDA + TRDA;
assign ADDER_B = TADD_B + TEMP_RDB + TRDB;
assign ADDER_C = TADD_C + TEMP_RDC + TRDC;
/////////////////////////////////////////////////////////////////
// TEMP_RDA,TEMP_RDB,TEMP_RDC (XA,YA,ZA)
/////////////////////////////////////////////////////////////////
always @(state or ADDER_A)begin
if (state == MUL_B)
begin
TEMP_RDA <= TADD_A;
end
else
begin
TEMP_RDA <= TEMP_RDA;
end
end
always @(state or ADDER_B)begin
if (state == MUL_C)
begin
TEMP_RDB <= TADD_B;
end
else
begin
TEMP_RDB <= TEMP_RDB;
end
end
always @(state or ADDER_C)begin
if (state == MUL_A)
begin
TEMP_RDC <= TADD_C;
end
else
begin
TEMP_RDC <= TEMP_RDC;
end
end
/////////////////////////////////////////////////////////////////
// TRDA,TRDB,TRDC;
/////////////////////////////////////////////////////////////////
always @(state or TADD_A)begin
if (state == ADD_B)begin
TRDA <= TADD_A;
end
else begin
TRDA <= TRDA;
end
end
always @(state or TADD_B)begin
if (state == ADD_C)begin
TRDB <= TADD_B;
end
else begin
TRDB <= TRDB;
end
end
always @(state or TADD_C)begin
if (state == ADD_A)begin
TRDC <= TADD_C;
end
else begin
TRDC <= TRDC;
end
end
reg [2:0] TAG_OUT;
always @(posedge CLK or negedge RST) begin
if(~RST)
TAG_OUT <= 3'b001;
else
if(state == ADD_B||state == ADD_A||state == ADD_C)
TAG_OUT <= IN_TAG;
else
TAG_OUT <= TAG_OUT;
end
reg [32:0] DX_OUT,DY_OUT,DZ_OUT;
always @(posedge CLK or negedge RST)begin
if(~RST)begin
DX_OUT <= 16'h0;
DY_OUT <= 16'h0;
DZ_OUT <= 16'h0;
end
else begin
case (state)
ADD_A: DY_OUT <= ADDER_B;
ADD_B: DZ_OUT <= ADDER_C;
ADD_C: DX_OUT <= ADDER_A;
default : begin
DY_OUT <= DY_OUT;
DZ_OUT <= DZ_OUT;
DX_OUT <= DX_OUT;
end
endcase
end
end
assign TAGOUT = TAG_OUT;
assign DXOUT = DX_OUT;
assign DYOUT = DY_OUT;
assign DZOUT = DZ_OUT;
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -