compute_pipe_rgb.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE MODULE *********************                                                                                                                      
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                                      
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                                                                                                                                                                                             
//************************************ Rev : V1.2	             *******************************************                                                                                                                                                                                                                                                                                      
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                                                                                                                                                                                                        
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                                                                                                                                                                                                        
//**************************************************************************************************************                                                                                                                                                                                                                                                                                        
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                                                                                                                                                                                                        
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                                      
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                                      
//**************************************************************************************************************                                                                                                                      
`timescale 1ns/1ns

module COMPUTE_PIPE_RGB(CLK, RST, REQ, TAGIN, A, B, DIN, TAGOUT, TAGVLD, DOUT );                                      
//input	signal   
input		CLK,RST,REQ;
input	[2:0]	TAGIN;
input	[7:0]	A,B;
input	[7:0]	DIN;
//output signal
output	[2:0]	TAGOUT;
output	[7:0]	DOUT;
output  	TAGVLD;
wire		TAGVLD;
wire	[2:0]	TAGOUT;
wire	[7:0]	DOUT;


COMPUTE_PIPE1 CPP(
		.CLK		(CLK	 ),
		.RST		(RST	 ),
		.REQ		(REQ	 ),
		.IN_TAG		(TAGIN	 ),
		.A		(A	 ),
		.B		(B	 ),
		.DIN		(DIN	 ),
		.TAGOUT		(TAGOUT	 ),
		.TAGVLD		(TAGVLD	 ),
		.DOUT		(DOUT	 )
	       );   
	       
endmodule