compute_pipe_t.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE MODULE *********************                                                                                                                                                             
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                                                                             
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                                                                             
//************************************ Rev : V1.2	             *******************************************                                                                                                                                                             
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                                                                             
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                                                                             
//**************************************************************************************************************                                                                                                                                                             
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                                                                             
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                                                                             
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                                                                             
//**************************************************************************************************************                                                                                                                                                             

`timescale 1ns/1ns 

module COMPUTE_PIPE_T();
reg 		RST,CLK;               
reg	[15:0]	A,B;                    
reg   		IN_TAG;                
reg	[15:0]	DIN;                   
reg 		REQ;                   
                                       
wire		W_OTAG, X_OTAG;
wire  	[32:0]	W_DOUT, X_DOUT;

always @(posedge CLK)begin
	IN_TAG = 1'b1;
end

initial                                 
begin                                   
#10 		CLK  <= 0;           
		RST  <= 0;           
		A = 8'h2;      
		B = 8'h1;  
		DIN <= 8'h4;	
#200		RST  <= 1;             
#50		REQ <= 1'b1;        
#50		REQ <= 1'b0;        
		                        
#500000 $stop;                          
end


initial                                                                                               
begin                                                            
     	$dumpfile("COMPUTE_PIPE_T.vcd");                         
        $dumpvars(0,COMPUTE_PIPE_T);                             
    	//$fsdbDumpfile("COMPUTE_PIPE_T.fsdb");                  
     	//$fsdbDumpvars(0,COMPUTE_PIPE_T);                       
#500000 $finish;	                                         
                                                                 
end //end initial                                                
                                                                 
//*********************************************************      
//                      TEST_sysclk                              
//*********************************************************      
                                                                 
always  #20  CLK <= !CLK;//clk -> 40us cycle time          

COMPUTE_PIPE PIPE (
		   .CLK		(CLK),
		   .RST		(RST),
		   .REQ		(REQ),
		   .IN_TAG	(IN_TAG),
		   .A		(A),
		   .B		(B),
		   .DIN		(DIN),
		   .W_OTAG	(W_OTAG),
		   .X_OTAG	(X_OTAG),
		   .W_DOUT	(W_DOUT),
		   .X_DOUT	(X_DOUT)       
		  );
endmodule