compute_pipe_ch3t.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************                                                                                                                                                                                                                          
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                                                                                                                                                  
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                                                                                                                                                  
//************************************ Rev : V1.2	             *******************************************                                                                                                                                                                                                                                  
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                                                                                                                                                  
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                                                                                                                                                  
//**************************************************************************************************************                                                                                                                                                                                                                                  
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                                                                                                                                                  
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                                                                                                                                                  
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                                                                                                                                                  
//**************************************************************************************************************
`timescale 1ns/1ns
 
module COMPUTE_PIPE_CH3T();
reg 		RST,CLK;               
reg	[15:0]	A,B,C;                    
wire   	[2:0]	IN_TAG;                
reg	[15:0]	X_DIN;
reg	[15:0]	Y_DIN;
reg	[15:0]	Z_DIN;                   
reg 		REQ;                   
                                       
wire	[2:0]	TAGOUT;
wire    [32:0]	DYOUT;
wire	[32:0]	DXOUT;
wire	[32:0]	DZOUT;

reg	clk;

always  @(posedge CLK or negedge RST)begin
	if (~RST)
	clk <= 1'b0;
	else
	clk <= ~clk;
end

reg	[15:0]	MEMX [255:0];
reg	[15:0]	MEMY [255:0];
reg	[15:0]	MEMZ [255:0];

parameter [2:0]	P0 = 3'b001,	
		P1 = 3'b100,
		P2 = 3'b010;
		
parameter 	ST0 = 2'b00,
		ST1 = 2'b01,
		ST2 = 2'b10;
				
reg	[1:0]ST,NEXT_ST;		

wire	DREQ = 1'b0;

always @(ST or DREQ)begin
	case (ST)
	ST0:	if (~DREQ)
		NEXT_ST = ST1;
		else
		NEXT_ST = ST0;
	ST1:	NEXT_ST = ST2;
	ST2:    NEXT_ST = ST0;
	default: NEXT_ST = ST0;
	endcase	
end

always @(posedge clk or negedge RST)begin
	if (~RST)
	ST <= ST0;
	else
	ST <= NEXT_ST;
end

reg	[2:0]	t;

always @(ST)begin
	case(ST)
	ST0: t <= P2;
	ST1: t <= P0;
	ST2: t <= P1;
	default: t<=t;
	endcase
end
	
assign IN_TAG = t;

reg	[7:0] a,b,c;                                          

always	@(posedge clk or negedge RST)begin
	if (~RST)begin
	a <= 8'h0;
	b <= 8'h0;
	c <= 8'h0;
	end
	else begin
	@(IN_TAG)
	case(1'b1)
	IN_TAG[2]: a <= a + 8'h1;
	IN_TAG[1]: b <= b + 8'h1;
	IN_TAG[0]: c <= c + 8'h1;
	endcase
	end
end

reg	[15:0] XD [255:0];
reg     [15:0] YD [255:0];
reg	[15:0] ZD [255:0];
	
integer i,j,k;

initial
begin
forever
begin
	  for (i =0;i< 256;i=i+1)begin
	  @(IN_TAG[2])begin
	  $readmemh("A.dat", MEMX);      
	  XD[i]  <= MEMX [i];
	  end              
	  end
end
end
	                         
initial
begin
forever
begin
	  for (j=0;j< 256;j=j+1)begin
	  @(IN_TAG[1])begin
	  $readmemh("B.dat", MEMY);      
	  YD[j] <= MEMY [j];
	  end
	  end
end
end

initial
begin
forever
begin
	  for (k=0;k< 256;k=k+1)begin
	  @(IN_TAG[0])begin
	  $readmemh("C.dat", MEMZ);      
	  ZD[k]  <= MEMZ [k];
	  end        
	  end      
end
end

always @(IN_TAG)begin
	case(1'b1)
	IN_TAG[2]: X_DIN <= XD[a];
	IN_TAG[1]: Y_DIN <= YD[b];
	IN_TAG[0]: Z_DIN <= ZD[c];
	endcase
end



initial                                 
begin                                   
#10 		CLK  <= 0;           
		RST  <= 0;           
		A <= 16'h1;      
		B <= 16'h2;  
		C <= 16'h3;
#200		RST  <= 1;             
#50		REQ <= 1'b1;        
#50		REQ <= 1'b0;        
		                        
#500000 $stop;                          
end


initial                                                                                               
begin                                                            
     	$dumpfile("COMPUTE_PIPE_CH3T.vcd");                         
        $dumpvars(0,COMPUTE_PIPE_CH3T);                             
    	//$fsdbDumpfile("COMPUTE_PIPE_CH3T.fsdb");                  
     	//$fsdbDumpvars(0,COMPUTE_PIPE_CH3T);                       
#500000 $finish;	                                         
                                                                 
end //end initial                                                
                                                                 
//*********************************************************      
//                      TEST_sysclk                              
//*********************************************************      
                                                                 
always  #20  CLK <= !CLK;//clk -> 40us cycle time          

COMPUTE_PIPE_CH3 PIPE3(
		   .CLK		(CLK),
		   .RST		(RST),
		   .REQ		(REQ),
		   //.DIN		(X_DIN),
		   .X_DIN	(X_DIN),
		   .Y_DIN	(Y_DIN),
		   .Z_DIN	(Z_DIN),	  
		   .IN_TAG	(IN_TAG),
		   .A		(A),
		   .B		(B),
		   .C		(C),
		   .TAGOUT	(TAGOUT),
		   .DXOUT	(DXOUT),
		   .DYOUT	(DYOUT),
		   .DZOUT  	(DZOUT)
		  );
endmodule
//******************************************************************************
//(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24
//(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30
//(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36
//******************************************************************************
//******************************************************************************
//(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(2 * 1) + (2 * 2) + (2 * 3)=2+4+6=12
//(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(1 * 1) + (1 * 2) + (1 * 3)=1+2+3=6
//(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(3 * 1) + (3 * 2) + (3 * 3)=3+6+9=18
//******************************************************************************