📄 compute_pipe.v
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//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************
//************************************ Copyright by @CDJ Co,.LTD *******************************************
//************************************ Dpt : ASIC R&D Dpt. *******************************************
//************************************ Rev : V1.2 *******************************************
//************************************ Author : Kevin Chiang *******************************************
//************************************ Modify : 2004/12/19 *******************************************
//**************************************************************************************************************
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********
//**************************************************************************************************************
// input => R-G-B-
// MAMAMA
// A B C =>output
//***********************************************************************************
`timescale 1ns/1ns
module COMPUTE_PIPE (CLK, RST, REQ, IN_TAG, A, B,DIN, W_OTAG, X_OTAG, W_DOUT, X_DOUT );
input RST,CLK;
input [15:0] A,B;
input IN_TAG;
input [15:0] DIN;
input REQ;
output W_OTAG, X_OTAG;
output [32:0] W_DOUT, X_DOUT;
reg [1:0] ST,ST_N;
parameter [1:0] ST0 = 2'b10,
ST1 = 2'b01;
parameter [1:0] ORDER_ST0 = 2'b00,
ORDER_ST1 = 2'b01;
always @(ST or REQ)begin
case (ST)
ORDER_ST0:
if (~REQ)
ST_N = ORDER_ST1;
else
ST_N = ORDER_ST0;
ORDER_ST1:ST_N = ORDER_ST0;
default: ST_N = ORDER_ST0;
endcase
end
always @(posedge CLK or negedge RST)begin
if (~RST)
ST = ORDER_ST0;
else
ST = ST_N;
end
reg [1:0] INTAG;
always @(posedge CLK)begin
case (ST)
ORDER_ST0: INTAG <= ST0;
ORDER_ST1: INTAG <= ST1;
default: INTAG<= INTAG;
endcase
end
////////////////////////////////////////////////////////////////
// W_DIN,Y_DIN,Z_DIN;
////////////////////////////////////////////////////////////////
reg [7:0] W_DIN,X_DIN;
always @(posedge CLK)begin
case (ST)
ORDER_ST0:W_DIN <=DIN;
ORDER_ST1:X_DIN <=DIN;
default: begin
W_DIN <= W_DIN;
X_DIN <= X_DIN;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// parameter of the registers
/////////////////////////////////////////////////////////////////////////////
reg [15:0] multiplicator_A,faciend_A;
reg [15:0] multiplicator_B,faciend_B;
reg [31:0] addend_A,summand_A;
reg [31:0] addend_B,summand_B;
wire [31:0] MULER_A,MULER_B;
wire [32:0] ADDER_A;
wire [31:0] MULER_C,MULER_D;
wire [32:0] ADDER_B;
wire [31:0] TADD_A;
wire [31:0] TADD_B;
reg [32:0] TRA;
reg [32:0] TRB;
//reg [7:0] A_DIN,B_DIN;
//////////////////////////////////////////////////////////////////////////////
reg [1:0] state,state_next;
parameter [1:0] MUL_A = 2'b00,
ADD_A = 2'b01,
MUL_B = 2'b10,
ADD_B = 2'b11;
always @(state or REQ ) begin
case (state)
MUL_A: begin
if (~REQ)
state_next = ADD_A;
else
state_next = MUL_A;
multiplicator_A <= W_DIN;
faciend_A <= A;
multiplicator_B <= TADD_B;
faciend_B <= B;
end
ADD_A: begin
state_next = MUL_B;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
MUL_B: begin
state_next = ADD_B;
multiplicator_A <= TADD_A;
faciend_A <= B;
multiplicator_B <= X_DIN;
faciend_B <= A;
end
ADD_B: begin
state_next = MUL_A;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
default: state_next = MUL_A;
endcase
end
always @(posedge CLK or negedge RST)begin
if (~RST)
state = MUL_A;
else
state = state_next;
end
//****************************MUL * 2 ********************************
//****************************ADD * 2 ********************************
assign MULER_A = multiplicator_A[31:16] * faciend_A;//A
assign MULER_B = multiplicator_A[15: 0] * faciend_A;//B
assign MULER_C = multiplicator_B[31:16] * faciend_B;//C
assign MULER_D = multiplicator_B[15:0] * faciend_B;//D
assign TADD_A = {addend_A,16'h0} + summand_A;
assign TADD_B = {addend_B,16'h0} + summand_B;
assign ADDER_A = TADD_A + TRA;
assign ADDER_B = TADD_B + TRB;
/*
////////////////////////////////////////////////////////////////////////
// process the INTAG point value
///////////////////////////////////////////////////////////////////////
//always @( state or INTAG or W_DIN or X_DIN)begin
always @(posedge CLK or negedge RST)begin
case (INTAG)
INTAG[1]: A_DIN = (state == MUL_A)? W_DIN:A_DIN;
INTAG[0]: B_DIN = (state == MUL_A)? X_DIN:B_DIN;
endcase
end
*/
/////////////////////////////////////////////////////////////////
// TEMP_RDA,TEMP_RDB;
/////////////////////////////////////////////////////////////////
reg [32:0] TEMP_RDA,TEMP_RDB;
always @(state or ADDER_B)begin
if (state == ADD_B)
begin
TEMP_RDA <= ADDER_A;
//TEMP_RDB <= ADDER_B;
end
else
begin
TEMP_RDA <= TEMP_RDB;
//TEMP_RDB <= TEMP_RDB;
end
end
always @(state or ADDER_B)begin
if (state == ADD_A)
begin
TEMP_RDB <= ADDER_B;
end
else
begin
TEMP_RDB <= TEMP_RDB;
end
end
/////////////////////////////////////////////////////////////////
// TADD_A,TADD_B;
/////////////////////////////////////////////////////////////////
always @(state or TADD_A)begin
if (state == ADD_A)begin
TRA <= TADD_A;
end
else begin
TRA <= TRA;
end
end
always @(state or TADD_B)begin
if (state == ADD_B)begin
TRB <= TADD_B;
end
else begin
TRB <= TRB;
end
end
/////////////////////////////////////////////////////////////////
// wotag,xotag;
/////////////////////////////////////////////////////////////////
reg wotag,xotag;
always @(state)begin
if (state == ADD_B)begin
wotag = 1'b1;
end
else
begin
wotag = 1'b0;
end
end
always @(state)begin
if (state == ADD_A)begin
xotag = 1'b1;
end
else
begin
xotag = 1'b0;
end
end
reg [32:0] A_DOUT,B_DOUT;
//always @(state or ADDER_A)begin
always @(posedge CLK)begin
A_DOUT = (state == ADD_B)? ADDER_A:A_DOUT;
end
//always @(state or ADDER_B)begin
always @(posedge CLK)begin
B_DOUT = (state == ADD_A)? ADDER_B:B_DOUT;
end
assign W_OTAG = wotag;
assign X_OTAG = xotag;
assign W_DOUT = A_DOUT;
assign X_DOUT = B_DOUT;
endmodule
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