compute_pipe_t2.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************                                                                                                               
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                               
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                               
//************************************ Rev : V1.2	             *******************************************                                                                                                               
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                               
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                               
//**************************************************************************************************************                                                                                                               
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                               
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                               
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                               
//**************************************************************************************************************                                                                                                               
//  		input => 	R-G-B-                                                                                                                                                                                         
//  				MAMAMA                                                                                                                                                                                         
//   				A B C =>output                                                                                                                                                                                 
//***********************************************************************************                                                                                                                                          

`timescale 1ns/1ns 

module COMPUTE_PIPE_T2();
reg 		RST,CLK;               
reg	[15:0]	A,B;                    
wire   	[1:0]	IN_TAG;                
reg	[15:0]	W_DIN;
reg	[15:0]	X_DIN;                   
reg 		REQ;                   
                                       
wire	[1:0]	TAGOUT;
wire    [32:0]	DOUT;
//wire	[32:0]	DXOUT;

reg	[1:0]	counter;

always  @(posedge CLK or negedge RST)begin
	if (~RST||counter == 2'b1)
	counter <= 2'b0;
	else
	counter <= counter + 2'b1;
end

reg	clk;

always @(counter)begin
	if (counter == 2'b1)
	clk <= 1'b1;	
	else
	clk <= 1'b0; 
end

parameter [1:0]	P0 = 2'b01,	
		P1 = 2'b10;
		
parameter 	ST0 = 1'b0,
		ST1 = 1'b1;		
reg	ST,NEXT_ST;		

wire	DREQ = 1'b0;

always @(ST or DREQ)begin
	case (ST)
	ST0:	if (~DREQ)
		NEXT_ST = ST1;
		else
		NEXT_ST = ST0;
	ST1:	NEXT_ST = ST0;
	default: NEXT_ST = ST0;
	endcase	
end

always @(posedge clk or negedge RST)begin
	if (~RST)
	ST <= ST0;
	else
	ST <= NEXT_ST;
end

reg	[1:0]	t;
always @(ST)begin
	case(ST)
	ST0: t <= P0;
	ST1: t <= P1;
	default: t<=t;
	endcase
end
	
assign IN_TAG = t;

initial                                 
begin                                   
#10 		CLK  <= 0;           
		RST  <= 0;           
		A <= 16'h2;      
		B <= 16'h1;  
		W_DIN <= 16'h4;
		X_DIN <= 16'h5;	
#200		RST  <= 1;             
#50		REQ <= 1'b1;        
#50		REQ <= 1'b0;        
		                        
#500000 $stop;                          
end


initial                                                                                               
begin                                                            
     	$dumpfile("COMPUTE_PIPE_T2.vcd");                         
        $dumpvars(0,COMPUTE_PIPE_T2);                             
    	//$fsdbDumpfile("COMPUTE_PIPE_T2.fsdb");                  
     	//$fsdbDumpvars(0,COMPUTE_PIPE_T2);                       
#500000 $finish;	                                         
                                                                 
end //end initial                                                
                                                                 
//*********************************************************      
//                      TEST_sysclk                              
//*********************************************************      
                                                                 
always  #20  CLK <= !CLK;//clk -> 40us cycle time          

COMPUTE_PIPE2  PIPE(
		   .CLK		(CLK),
		   .RST		(RST),
		   .REQ		(REQ),
		   .W_DIN	(W_DIN),
		   .X_DIN	(X_DIN),	  
		   .IN_TAG	(IN_TAG),
		   .A		(A),
		   .B		(B),
		   .TAGOUT	(TAGOUT),
		   //.DOUT	(DWOUT),
		   .DOUT	(DOUT)
		  );
endmodule