📄 compute_pipe2.v
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//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************
//************************************ Copyright by @CDJ Co,.LTD *******************************************
//************************************ Dpt : ASIC R&D Dpt. *******************************************
//************************************ Rev : V1.2 *******************************************
//************************************ Author : Kevin Chiang *******************************************
//************************************ Modify : 2004/12/19 *******************************************
//**************************************************************************************************************
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********
//**************************************************************************************************************
// input => R-G-B-
// MAMAMA
// A B C =>output
//***********************************************************************************
`timescale 1ns/1ns
module COMPUTE_PIPE2 (CLK, RST, REQ, IN_TAG, W_DIN, X_DIN, A, B, TAGOUT, DOUT);//DXOUT);
//input signal
input RST,CLK;
input [15:0] A,B;
input [1:0] IN_TAG;
input [15:0] W_DIN;
input [15:0] X_DIN;
input REQ;
//output signal
output TAGOUT;
//output [32:0] DWOUT;
output [32:0] DOUT;
wire [1:0] TAGOUT;
//wire [32:0] DXOUT;
wire [32:0] DOUT;
/*
////////////////////////////////////////////////////////////////
// W_DIN,X_DIN
////////////////////////////////////////////////////////////////
reg [15:0] W_DIN,X_DIN;
always @(posedge CLK or negedge RST)begin
if (~RST)
begin
W_DIN <= 16'h0;
X_DIN <= 16'h0;
end
else begin
case (IN_TAG)
IN_TAG[1] : W_DIN <= DIN;
IN_TAG[0] : X_DIN <= DIN;
endcase
end
end
*/
/////////////////////////////////////////////////////////////////////////////
// parameter of the registers
/////////////////////////////////////////////////////////////////////////////
reg [15:0] multiplicator_A,faciend_A;
reg [15:0] multiplicator_B,faciend_B;
reg [15:0] addend_A,summand_A;
reg [15:0] addend_B,summand_B;
wire [31:0] MULER_A,MULER_B;
wire [32:0] ADDER_A;
wire [31:0] MULER_C,MULER_D;
wire [32:0] ADDER_B;
wire [31:0] TADD_A;
wire [31:0] TADD_B;
reg [31:0] TRA;
reg [31:0] TRB;
reg [24:0] TEMP_RDA,TEMP_RDB;
//////////////////////////////////////////////////////////////////////////////
reg [1:0] state,state_next;
parameter [1:0] MUL_A = 2'b00,
ADD_A = 2'b01,
MUL_B = 2'b10,
ADD_B = 2'b11;
always @(state or REQ ) begin
case (state)
MUL_A: begin
if (~REQ)
state_next = ADD_A;
else
state_next = MUL_A;
multiplicator_A <= W_DIN;
faciend_A <= A;
multiplicator_B <= TEMP_RDB;
faciend_B <= B;
end
ADD_A: begin
state_next = MUL_B;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
MUL_B: begin
state_next = ADD_B;
multiplicator_A <= TEMP_RDA;
faciend_A <= B;
multiplicator_B <= X_DIN;
faciend_B <= A;
end
ADD_B: begin
state_next = MUL_A;
addend_A <= MULER_A;
summand_A <= MULER_B;
addend_B <= MULER_C;
summand_B <= MULER_D;
end
default: state_next = MUL_A;
endcase
end
always @(posedge CLK or negedge RST)begin
if (~RST)
state = MUL_A;
else
state = state_next;
end
//****************************MUL * 2 ********************************
//****************************ADD * 2 ********************************
assign MULER_A = multiplicator_A[31:16] * faciend_A;//A
assign MULER_B = multiplicator_A[15:0] * faciend_A;//B
assign MULER_C = multiplicator_B[31:16] * faciend_B;//C
assign MULER_D = multiplicator_B[15:0] * faciend_B;//D
assign TADD_A = {addend_A,16'h0} + summand_A;
assign TADD_B = {addend_B,16'h0} + summand_B;
assign ADDER_A = TADD_A + TRA;
assign ADDER_B = TADD_B + TRB;
/////////////////////////////////////////////////////////////////
// TEMP_RDA,TEMP_RDB;
/////////////////////////////////////////////////////////////////
always @(posedge CLK )begin
if (state == ADD_B)
begin
TEMP_RDA <= ADDER_A;
end
else
begin
TEMP_RDA <= TEMP_RDB;
end
end
always @(posedge CLK)begin
if (state == ADD_A)
begin
TEMP_RDB <= ADDER_B;
end
else
begin
TEMP_RDB <= TEMP_RDB;
end
end
/////////////////////////////////////////////////////////////////
// TADD_A,TADD_B;
/////////////////////////////////////////////////////////////////
always @(posedge CLK)begin
if (state == ADD_A)begin
TRA <= TADD_A;
end
else begin
TRA <= TRA;
end
end
always @(posedge CLK)begin
if (state == ADD_B)begin
TRB <= TADD_B;
end
else begin
TRB <= TRB;
end
end
/////////////////////////////////////////////////////////////////
// wotag,xotag;
/////////////////////////////////////////////////////////////////
reg tagout;
always @(posedge CLK or negedge RST)begin
if(~RST)
tagout = 1'b0;
else
tagout = (ADD_A || ADD_B )? 1'b1:1'b0;
end
reg [1:0] TAG_OUT;
always @(posedge CLK or negedge RST) begin
if(~RST)
TAG_OUT <= 2'b01;
else
if(state == ADD_B || state == ADD_A)
TAG_OUT <= IN_TAG;
else
TAG_OUT <= TAG_OUT;
end
reg [32:0] D_OUT;//,DX_OUT;
always @(posedge CLK)begin
if(~RST)begin
D_OUT <= 16'h0;
//DX_OUT <= 16'h0;
end
else begin
case (TAG_OUT)
1'b1: D_OUT <= ADDER_B;
1'b0: D_OUT <= ADDER_A;
default : begin
D_OUT <= D_OUT;
//DW_OUT <= DW_OUT;
end
endcase
end
end
assign TAGOUT = TAG_OUT;
//assign DWOUT = DW_OUT;
assign DOUT = D_OUT;
//assign DXOUT = DX_OUT;
endmodule
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