compute_pipe_rgb_t.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************                                                                                                                    
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                                      
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                                      
//************************************ Rev : V1.2	             *******************************************                                                                                                                      
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                                      
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                                      
//**************************************************************************************************************                                                                                                                      
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                                      
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                                      
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                                      
//**************************************************************************************************************                                                                                                                      

`timescale 1ns/1ns 

module COMPUTE_PIPE_RGB_T();
reg 		RST,CLK;               
reg	[7:0]	A,B;                    
wire   	[2:0]	TAGIN;                
reg	[7:0]	DIN;                   
reg 		REQ;                   
                                       
wire	[2:0]	TAGOUT;
wire  	[7:0]	DOUT;
wire		TAGVLD;
//****************************************************************************
reg	[1:0]	counter;                                   
                                                           
reg		clk;                                       
                                                           
always @(posedge CLK or negedge RST)begin              
	if (~RST ||counter ==2'b01)                        
	counter<=2'b0;                                     
	else                                               
	counter<= counter + 2'b1;                          
end                                                        
                                                           
always @(counter)begin                                     
	if (counter == 2'b01)                               
	clk <= 1'b1;                                       
	else                                               
	clk <= 1'b0;                                       
end                                                        
                                                           
                                                           
                                                           
parameter [1:0] BV_ST1	=		3'b001,            
		BV_ST2	=		3'b010,            
		BV_ST4	=		3'b100;            
                                                           
parameter [4:0] B_ST0	=		2'b00,             
		B_ST1	=		2'b01,             
		B_ST2	=		2'b10,             
		B_ST3	=		2'b11;             
                                                           
reg [1:0] state,state_next;                                
                                                           
wire	DREQ = 1'b0;                                        
                                                           
always @(state or REQ) begin                               
	case (state)                                       
	B_ST0: 	                                           
			if (~DREQ)                          
			state_next = B_ST1;                
			else                               
			state_next = B_ST0;	           
	B_ST1:		      		                   
                        state_next = B_ST2;                
        B_ST2:                                             
        	        state_next = B_ST3;	           
  	B_ST3:                                             
         	        state_next = B_ST1;                
	default:	state_next = B_ST0;                
	endcase                                            
	                                                   
end                                                        
                                                           
always @(posedge clk or negedge RST)begin                 
	if (~RST)                                         
	state = B_ST0;                                     
	else                                               
	state = state_next;                                
end                                                        
                                                           
reg	[2:0]	tag;	                                   
	                                                   
always @(state)begin                                       
	case (state)                                       
	B_ST0:  tag = tag;                                 
	B_ST1:  tag = BV_ST4;                              
        B_ST2:  tag = BV_ST2;                              
	B_ST3:  tag = BV_ST1; 	                           
	default: tag = tag;                                
	endcase                                            
end                                                        
                                                           
wire    [2:0]   t = tag;                                   

assign 	TAGIN = tag;                                      
//*********************************************************************

initial                                 
begin                                   
#10 		CLK  <= 0;           
		RST  <= 0;           
		A = 8'h2;      
		B = 8'h1;  
		DIN <= 8'h4;	
#200		RST  <= 1;             
#50		REQ <= 1'b1;        
#50		REQ <= 1'b0;        
		                        
#500000 $stop;                          
end


initial                                                                                               
begin                                                            
     	$dumpfile("COMPUTE_PIPE_RGB_T.vcd");                         
        $dumpvars(0,COMPUTE_PIPE_RGB_T);                             
    	//$fsdbDumpfile("COMPUTE_PIPE_RGB_T.fsdb");                  
     	//$fsdbDumpvars(0,COMPUTE_PIPE_RGB_T);                       
#500000 $finish;	                                         
                                                                 
end //end initial                                                
                                                                 
//*********************************************************      
//                      TEST_sysclk                              
//*********************************************************      
                                                                 
always  #20  CLK <= !CLK;//clk -> 40us cycle time          

COMPUTE_PIPE_RGB PIPE(
		     .CLK		(CLK),
		     .RST		(RST),
		     .REQ		(REQ),
		     .TAGIN		(TAGIN),
		     .A			(A),
		     .B			(B),
		     .DIN		(DIN),
		     .TAGOUT		(TAGOUT),
		     .TAGVLD		(TAGVLD),
		     .DOUT		(DOUT)
		  );
endmodule