comp_pipe_rgb.v

利用2個加法器及2個乘法器加上平行化處理來實現

//************************************ The Module is for PIPELINE of MUL_ADD DEVICE testing MODULE *************                                                                                                               
//************************************ Copyright by @CDJ Co,.LTD     *******************************************                                                                                                               
//************************************ Dpt : ASIC R&D Dpt.           *******************************************                                                                                                               
//************************************ Rev : V1.2	             *******************************************                                                                                                               
//************************************ Author : Kevin Chiang 	     *******************************************                                                                                                               
//************************************ Modify : 2004/12/19	     *******************************************                                                                                                               
//**************************************************************************************************************                                                                                                               
//**********************(XDIN * A)+ (XDIN * A) * B + (XDIN * C)=(4 * 1) + (4 * 2) + (4 * 3)=4+8+12=24 **********                                                                                                               
//**********************(YDIN * A)+ (YDIN * A) * B + (YDIN * C)=(5 * 1) + (5 * 2) + (5 * 3)=5+10+15=30**********                                                                                                               
//**********************(ZDIN * A)+ (ZDIN * A) * B + (ZDIN * C)=(6 * 1) + (6 * 2) + (6 * 3)=6+12+18=36**********                                                                                                               
//**************************************************************************************************************                                                                                                               
//  		input => 	R-G-B-                                                                                                                                                                                         
//  				MAMAMA                                                                                                                                                                                         
//   				A B C =>output                                                                                                                                                                                 
//***********************************************************************************                                                                                                                                          

`timescale 1ns/1ns 

module COMPUTE_PIPE_RGB (CLK, RST, REQ, TAGIN, A, B, DIN, TAGOUT, DOUT );                                      
//input	signal   
input		CLK,RST,REQ;
input	[2:0]	TAGIN;
input	[7:0]	A,B;
input	[7:0]	DIN;
//output signal
output	[2:0]	TAGOUT;
output	[7:0]	DOUT;

wire	[2:0]	TAGOUT;
wire	[7:0]	RDOUT;
wire	[7:0]	GDOUT; 
wire	[7:0]	BDOUT; 
reg     [7:0]	dout;
reg	[7:0]	din;



always @(TAGIN)begin
	case (TAGIN)
	TAGIN[2]: din = DIN;   
	TAGIN[1]: din = DIN;   
	TAGIN[0]: din = DIN;   
        default  : din = din;    
        endcase    
end
                        
always @(TAGOUT)begin
	case (TAGOUT)
	TAGOUT[2]: dout = RDOUT;
	TAGOUT[1]: dout = GDOUT;
	TAGOUT[0]: dout = BDOUT;
	default  : dout = dout;
	endcase
end	

COMPUTE_PIPE1 PR(
		.CLK		(CLK	 ),
		.RST		(RST	 ),
		.REQ		(REQ	 ),
		.IN_TAG		(TAGIN[2]),
		.A		(A	 ),
		.B		(B	 ),
		.DIN		(din	 ),
		.TAGOUT		(TAGOUT[2]),
		.DOUT		(RDOUT	 )
	       );   

COMPUTE_PIPE1 PG(                                 
 		.CLK		(CLK	 ),      
 		.RST		(RST	 ),      
 		.REQ		(REQ	 ),      
 		.IN_TAG		(TAGIN[1]),      
 		.A		(A	 ),      
 		.B		(B	 ),      
 		.DIN		(din	 ),      
 		.TAGOUT		(TAGOUT[1]),      
 		.DOUT		(GDOUT )       
 	       );                                
 	       
COMPUTE_PIPE1 PB(                                  	       
		.CLK		(CLK	 ),      
		.RST		(RST	 ),      
		.REQ		(REQ	 ),      
		.IN_TAG		(TAGIN[0]),      
		.A		(A	 ),      
		.B		(B	 ),      
		.DIN		(din	 ),      
		.TAGOUT		(TAGOUT[0]),      
		.DOUT		(BDOUT	 )       
	       );                       
endmodule