keyexpansion.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : keyexpansion.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: KeyExpansion entity
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity keyexpansion is
  port(
    clk : in std_logic;

    -- key i/o
    key_in     : in  std_logic_vector (7 downto 0);  -- external key input
    key_out    : out std_logic_vector (7 downto 0);
    key_d4_out : out std_logic_vector (7 downto 0);  -- delayed key output

    -- i/o to external (forward) bytesubstitution (sbox)
    data_to_sbox_out  : out std_logic_vector (7 downto 0);
    data_from_sbox_in : in  std_logic_vector (7 downto 0);

    -- control inputs
    load_in    : in std_logic;
    shift_in   : in std_logic;
    inverse_in : in std_logic;
    seq_in     : in std_logic_vector(3 downto 0);  -- sequence counter

    -- current round number
    round_in : in std_logic_vector (3 downto 0)
    );
end keyexpansion;