par2ser.vhd

来自「VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA」· VHDL 代码 · 共 78 行

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : par2ser.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: Simple Parallel to Serial converter
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity par2ser is
  
  port (
    clk : in std_logic;

    load_par_in : in std_logic;
    load_ser_in : in std_logic;
    shift_in    : in std_logic;

    data_serial_in  : in  std_logic_vector(7 downto 0);
    data_serial_out : out std_logic_vector(7 downto 0);

    data_parallel0_in : in std_logic_vector(7 downto 0);
    data_parallel1_in : in std_logic_vector(7 downto 0);
    data_parallel2_in : in std_logic_vector(7 downto 0);
    data_parallel3_in : in std_logic_vector(7 downto 0));

end entity par2ser;

architecture rtl of par2ser is

  signal sreg0_r, sreg1_r, sreg2_r, sreg3_r : std_logic_vector(7 downto 0);

begin  -- architecture rtl

  -- output multiplexer
  data_serial_out <= data_parallel0_in when load_par_in = '1' else
                     sreg0_r;

  clocked : process (clk) is
  begin  -- process clocked
    if rising_edge(clk) then            -- rising clock edge

      -- check if control signal conditions are violated
      -- (simulation only)
      assert ((load_ser_in and shift_in) /= '1')
        report "load_ser_in = shift_in = '1'" severity warning;
      assert ((load_par_in and load_ser_in) /= '1')
        report "load_par_in = load_ser_in = '1'" severity warning;

      if (load_par_in = '1') then
        sreg0_r <= data_parallel1_in;
        sreg1_r <= data_parallel2_in;
        sreg2_r <= data_parallel3_in;
      elsif (shift_in = '1' or load_ser_in = '1') then
        sreg0_r <= sreg1_r;
        sreg1_r <= sreg2_r;
        sreg2_r <= sreg3_r;
      end if;

      if (load_ser_in = '1') then
        sreg3_r <= data_serial_in;
      end if;

    end if;
  end process clocked;
  
end architecture rtl;