subbytes.vhd

来自「VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA」· VHDL 代码 · 共 50 行

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : subbytes.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: SubBytes (S-box) entity.
--
-- subbytes is bidirectional
-- fwd_subbytes is forward only
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity subbytes is
  generic(
    pipeline_length_g : integer := 0
    );
  port(
    clk        : in  std_logic;
    inverse_in : in  std_logic;         -- '1' = inverse subbytes
    data_in    : in  std_logic_vector (7 downto 0);
    data_out   : out std_logic_vector (7 downto 0)
    );
end subbytes;

library ieee;
use ieee.std_logic_1164.all;

-- forward sbox
entity fwd_subbytes is
  generic(
    pipeline_length_g : integer := 0
    );
  port(
    clk        : in  std_logic;
    data_in    : in  std_logic_vector (7 downto 0);
    data_out   : out std_logic_vector (7 downto 0)
    );
end fwd_subbytes;