keyexpansion_fwd_rtl.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : keyexpansion_fwd_rtl.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: KeyExpansion architecture (forward operation only)
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------
-- FORWARD ONLY
-------------------------------------------------------------------------------

architecture fwd_rtl of keyexpansion is

  type control_seq_t is array (0 to 15) of integer range 0 to 4;
  constant control_seq : control_seq_t := (1, 2, 2, 3, 0, 0, 0, 0,
                                           0, 0, 0, 0, 4, 4, 4, 4);
  signal sequence : integer range 0 to 15;

  type shiftreg_t is array (0 to 15) of std_logic_vector(7 downto 0);

  signal shift_r    : shiftreg_t;
  signal rcon_value : std_logic_vector(7 downto 0);

  -- storage for key byte required for RotWord() -operation.
  signal rotword_r : std_logic_vector(7 downto 0);

  signal d0, d1, d2 : std_logic;        -- mux control signals
  signal d3         : std_logic;        -- '1' = signal "rcon_value" is zeroed

  -- key byte output (also fed back to shift register) 
  signal key_out_int : std_logic_vector(7 downto 0);

  signal ext_control : std_logic_vector(1 downto 0);
  
begin  -- architecture rtl

  key_out    <= key_out_int;
  key_d4_out <= shift_r(12);

  --mux0
  data_to_sbox_out <= shift_r(13) when d0 = '1' else
                      rotword_r;
  --mux1 and rcon xor
  key_out_int <= data_from_sbox_in xor rcon_value xor shift_r(0)
                 when (d1 = '1' and d3 = '0') else
                 data_from_sbox_in xor shift_r(0)
                 when (d1 = '1' and d3 = '1') else
                 shift_r(0);

  ext_control(1) <= load_in;
  ext_control(0) <= shift_in;

  sequence <= to_integer(unsigned(seq_in));


  -- inverse is not implemented in this architecture
  assert (inverse_in /= '1') report "inverse operation not supported" severity warning;

  ---------------------------------------------+
  --             |          control            |
  --             |  0  |  1  |  2  |  3  |  4  |
  ---------------+-----+-----+-----+-----+-----|
  --    d0       |  0  |  1  |  1  |  0  |  0  |
  --    d1       |  0  |  1  |  1  |  1  |  0  |
  --    d2       |  0  |  0  |  0  |  0  |  1  |
  --    d3       |  1  |  0  |  1  |  1  |  1  |
  ---------------------------------------------+
  muxcontrol : process (sequence) is
  begin  -- process muxcontrol
    case control_seq(sequence) is
      when 0 =>
        d0 <= '0';
        d1 <= '0';
        d2 <= '0';
        d3 <= '1';
        
      when 1 =>
        d0 <= '1';
        d1 <= '1';
        d2 <= '0';
        d3 <= '0';

      when 2 =>
        d0 <= '1';
        d1 <= '1';
        d2 <= '0';
        d3 <= '1';

      when 3 =>
        d0 <= '0';
        d1 <= '1';
        d2 <= '0';
        d3 <= '1';

      when others =>                    -- when 4 =>
        d0 <= '0';
        d1 <= '0';
        d2 <= '1';
        d3 <= '1';
        
    end case;
  end process muxcontrol;

  --shift register
  shifter : process (clk) is
  begin
    if rising_edge(clk) then            -- rising clock edge
      case ext_control is
        when "00" =>                    -- stall

        when "01" =>                    -- shift
          shift_r(15) <= key_out_int;
          if (d2 = '0') then
            shift_r(3) <= key_out_int xor shift_r(4);
          else
            shift_r(3) <= shift_r(4);
          end if;
          
        when "10" =>                    -- load
          shift_r(15) <= key_in;
          shift_r(3)  <= shift_r(4);
          
        when others =>                  -- load and shift, (used during
                                        -- simultaneous loading and unloading)
          shift_r(15) <= key_in;
          if (d2 = '0') then
            shift_r(3) <= key_out_int xor shift_r(4);
          else
            shift_r(3) <= shift_r(4);
          end if;

      end case;

      if (shift_in = '1' or load_in = '1') then
        for i in 4 to 14 loop
          shift_r(i) <= shift_r(i+1);
        end loop;  -- i

        for i in 0 to 2 loop
          shift_r(i) <= shift_r(i+1);
        end loop;  -- i

      end if;

      if (sequence = 0) then
        rotword_r <= shift_r(12);
      end if;

    end if;
  end process shifter;

-- round constant "calculation"
  rcon : process (round_in) is
  begin  -- process rcon
    case round_in is
      when "0000" =>
        rcon_value <= std_logic_vector(to_unsigned(16#01#, 8));
      when "0001" =>
        rcon_value <= std_logic_vector(to_unsigned(16#02#, 8));
      when "0010" =>
        rcon_value <= std_logic_vector(to_unsigned(16#04#, 8));
      when "0011" =>
        rcon_value <= std_logic_vector(to_unsigned(16#08#, 8));
      when "0100" =>
        rcon_value <= std_logic_vector(to_unsigned(16#10#, 8));
      when "0101" =>
        rcon_value <= std_logic_vector(to_unsigned(16#20#, 8));
      when "0110" =>
        rcon_value <= std_logic_vector(to_unsigned(16#40#, 8));
      when "0111" =>
        rcon_value <= std_logic_vector(to_unsigned(16#80#, 8));
      when "1000" =>
        rcon_value <= std_logic_vector(to_unsigned(16#1b#, 8));
      when "1001" =>
        rcon_value <= std_logic_vector(to_unsigned(16#36#, 8));
      when others =>
        rcon_value <= (others => '-');
    end case;
  end process rcon;

end architecture fwd_rtl;