bytepermutation_fwd_rtl.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : bytepermutation_fwd_rtl.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: BytePermutation architecture (forward only)
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------
-- The idea of this byte permutation unit is originally presented in:
-- Tuomas J鋜vinen, Perttu Salmela, Panu H鋗鋖鋓nen, Jarmo Takala,
-- "Efficient Byte Permutation Realizations for Compact AES
-- Implementations", 13th European Signal Processing Conference
-- (EUSIPCO 2005), Antalya, Turkey, September 4-8, 2005.
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- FORWARD ONLY (i.e. encryption)
-------------------------------------------------------------------------------
architecture fwd_rtl of bytepermutation is

  type control_seq_t is array (0 to 15) of integer range 0 to 3;

  constant forward_seq : control_seq_t := (3, 2, 1, 0, 3, 2, 1, 1,
                                           3, 2, 3, 2, 3, 3, 3, 3);

  signal sequence     : integer range 0 to 15;
  signal control_word : integer range 0 to 3;

  type sreg_t is array (0 to 3) of std_logic_vector(7 downto 0);

  signal sreg0_r, sreg1_r, sreg2_r : sreg_t;
  -- mux control signals
  signal c0, c1, c2                : std_logic;  
  -- (output) mux control signal
  signal c3 : std_logic_vector(1 downto 0);  

  signal ext_control : std_logic_vector(1 downto 0);
begin  -- architecture rtl

  assert (inverse_in /= '1') report "this architecture supports only forward operation"
    severity failure;

  --output mux (c3)
  data_out <= data_in when c3 = "00" else
              sreg0_r(3) when c3 = "01" else
              sreg1_r(3) when c3 = "10" else
              sreg2_r(3);

  ext_control(1) <= load_in;
  ext_control(0) <= shift_in;

  sequence <= to_integer(unsigned(seq_in));
  control_word <= forward_seq(sequence);

  muxcontrol : process (control_word) is
  begin  -- process muxcontrol

    case control_word is
      when 0 =>
        c0 <= '1';
        c1 <= '0';
        c2 <= '0';
        c3 <= "00";

      when 1 =>
        c0 <= '0';
        c1 <= '1';
        c2 <= '0';
        c3 <= "01";

      when 2 =>
        c0 <= '0';
        c1 <= '0';
        c2 <= '1';
        c3 <= "10";

      when others =>                    -- when 3 =>
        c0 <= '0';
        c1 <= '0';
        c2 <= '0';
        c3 <= "11";

    end case;
  end process muxcontrol;

  shift_reg : process (clk) is
  begin
    if rising_edge(clk) then            -- rising clock edge

      case ext_control is
        when "01" | "11" =>             -- shift, or load and shift
          if (c0 = '1') then
            sreg0_r(0) <= sreg2_r(3);
          else
            sreg0_r(0) <= data_in;
          end if;
          if (c1 = '1') then
            sreg1_r(0) <= sreg2_r(3);
          else
            sreg1_r(0) <= sreg0_r(3);
          end if;
          if (c2 = '1') then
            sreg2_r(0) <= sreg2_r(3);
          else
            sreg2_r(0) <= sreg1_r(3);
          end if;
          
        when "10" =>                    -- load
          sreg0_r(0) <= data_in;
          sreg1_r(0) <= sreg0_r(3);
          sreg2_r(0) <= sreg1_r(3);

        when others =>                  -- stall
          
      end case;

      if (ext_control /= "00") then     -- if not 'stall'
        for i in 1 to 3 loop
          sreg0_r(i) <= sreg0_r(i-1);
          sreg1_r(i) <= sreg1_r(i-1);
          sreg2_r(i) <= sreg2_r(i-1);
        end loop;  -- i
      end if;
      
    end if;
  end process shift_reg;

end architecture fwd_rtl;