aes_tb_test1.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : aes_tb_test1.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: Testbench for design "aes"
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


architecture test1 of aes_tb is

  component aes
    port (
      clk        : in  std_logic;
      rst_n      : in  std_logic;
      data_in    : in  std_logic_vector(7 downto 0);
      data_out   : out std_logic_vector(7 downto 0);
      key_in     : in  std_logic_vector(7 downto 0);
      load_in    : in  std_logic;
      unload_in  : in  std_logic;
      start_in   : in  std_logic;
      inverse_in : in  std_logic;
      busy_out   : out std_logic);
  end component;

  -- component ports
  signal clk        : std_logic := '0';
  signal rst_n      : std_logic;
  signal data_in    : std_logic_vector(7 downto 0);
  signal data_out   : std_logic_vector(7 downto 0);
  signal key_in     : std_logic_vector(7 downto 0);
  signal load_in    : std_logic;
  signal unload_in  : std_logic;
  signal start_in   : std_logic;
  signal inverse_in : std_logic;
  signal busy_out   : std_logic;

  constant test_inverse : std_logic := '0';
  constant ntests       : integer   := 2;  -- number of tests
  type     testvec_t is array (0 to 15) of integer range 0 to 255;
  type     testvec_arr_t is array (0 to ntests-1) of testvec_t;

  constant key_fwd : testvec_arr_t :=
    (
      (16#00#, 16#01#, 16#02#, 16#03#, 16#04#, 16#05#, 16#06#, 16#07#,
       16#08#, 16#09#, 16#0a#, 16#0b#, 16#0c#, 16#0d#, 16#0e#, 16#0f#),

      (16#2b#, 16#7e#, 16#15#, 16#16#, 16#28#, 16#ae#, 16#d2#, 16#a6#,
       16#ab#, 16#f7#, 16#15#, 16#88#, 16#09#, 16#cf#, 16#4f#, 16#3c#) 
      );

  constant key_inv : testvec_arr_t :=
    (
      (16#13#, 16#11#, 16#1d#, 16#7f#, 16#e3#, 16#94#, 16#4a#, 16#17#,
       16#f3#, 16#07#, 16#a7#, 16#8b#, 16#4d#, 16#2b#, 16#30#, 16#c5#),

      (16#d0#, 16#14#, 16#f9#, 16#a8#, 16#c9#, 16#ee#, 16#25#, 16#89#,
       16#e1#, 16#3f#, 16#0c#, 16#c8#, 16#b6#, 16#63#, 16#0c#, 16#a6#)
      );
  constant ptext : testvec_arr_t :=
    (
      (16#00#, 16#11#, 16#22#, 16#33#, 16#44#, 16#55#, 16#66#, 16#77#,
       16#88#, 16#99#, 16#aa#, 16#bb#, 16#cc#, 16#dd#, 16#ee#, 16#ff#),
      
      (16#32#, 16#43#, 16#f6#, 16#a8#, 16#88#, 16#5a#, 16#30#, 16#8d#,
       16#31#, 16#31#, 16#98#, 16#a2#, 16#e0#, 16#37#, 16#07#, 16#34#)
      );
  constant ctext : testvec_arr_t :=
    (
      (16#69#, 16#c4#, 16#e0#, 16#d8#, 16#6a#, 16#7b#, 16#04#, 16#30#,
       16#d8#, 16#cd#, 16#b7#, 16#80#, 16#70#, 16#b4#, 16#c5#, 16#5a#),

      (16#39#, 16#25#, 16#84#, 16#1d#, 16#02#, 16#dc#, 16#09#, 16#fb#,
       16#dc#, 16#11#, 16#85#, 16#97#, 16#19#, 16#6a#, 16#0b#, 16#32#)
      );

begin  -- architecture test1

  DUT : aes
    port map (
      clk        => clk,
      rst_n      => rst_n,
      data_in    => data_in,
      data_out   => data_out,
      key_in     => key_in,
      load_in    => load_in,
      unload_in  => unload_in,
      start_in   => start_in,
      inverse_in => inverse_in,
      busy_out   => busy_out);

  -- clock generation
  clk <= not clk after 5 ns;          -- 100 MHz clock

  gen_reset : process
  begin
    rst_n <= '0';
    wait for 10 ns;
    rst_n <= '1';
    wait;
  end process gen_reset;


  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    data_in   <= (others => '0');
    key_in    <= (others => '0');
    load_in   <= '0';
    unload_in <= '0';

    inverse_in <= '0';
    start_in   <= '0';

    wait until rising_edge(clk) and rst_n = '1';

    --few idle cycles
    for t in 0 to 1 loop
      wait until rising_edge(clk);
    end loop;  -- t
    
    for t in 0 to ntests-1 loop
      -------------------------------------------------------------------------
      -- encrypt
      -------------------------------------------------------------------------
      -- load input
      for i in 0 to 15 loop
        wait until falling_edge(clk);
        inverse_in <= '0';
        load_in    <= '1';
        data_in <= std_logic_vector(to_unsigned(ptext(t)(i), 8));
        key_in  <= std_logic_vector(to_unsigned(key_fwd(t)(i), 8));
      end loop;  -- i
      wait until falling_edge(clk);
      load_in  <= '0';
      start_in <= '1';
      wait until falling_edge(clk);
      start_in <= '0';

      -- compute
      wait until rising_edge(clk) and busy_out = '0';

      -- read output & check result
      wait until falling_edge(clk);
      unload_in <= '1';
      for i in 0 to 15 loop
        wait until rising_edge(clk);
        assert ctext(t)(i) = to_integer(unsigned(data_out))
          report "forward failed" severity error;
      end loop;  -- i
      unload_in <= '0';
      wait until rising_edge(clk);

      if (test_inverse = '1') then
        -----------------------------------------------------------------------
        -- decrypt
        -----------------------------------------------------------------------
        -- load input
        inverse_in <= '1';
        load_in    <= '1';
        for i in 0 to 15 loop
          data_in <= std_logic_vector(to_unsigned(ctext(t)(i), 8));
          key_in  <= std_logic_vector(to_unsigned(key_inv(t)(i), 8));
          wait until rising_edge(clk);
        end loop;  -- i
        load_in  <= '0';
        start_in <= '1';
        wait until rising_edge(clk);
        start_in <= '0';

        -- compute
        wait until rising_edge(clk) and busy_out = '0';

        -- read output & check result
        unload_in <= '1';
        for i in 0 to 15 loop
          wait until rising_edge(clk);
          wait for 1 ns;
          assert ptext(t)(i) = to_integer(unsigned(data_out))
            report "inverse failed" severity error;
        end loop;  -- i      
        unload_in <= '0';
        wait until rising_edge(clk);
        
      end if;

    end loop;  -- t

    report "tests done!" severity warning;
    wait;
  end process WaveGen_Proc;

  

end architecture test1;