aes_tb_test3.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : aes_tb_test3.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: Testbench for design "aes"
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


architecture test3 of aes_tb is

  component aes
    port (
      clk        : in  std_logic;
      rst_n      : in  std_logic;
      data_in    : in  std_logic_vector(7 downto 0);
      data_out   : out std_logic_vector(7 downto 0);
      key_in     : in  std_logic_vector(7 downto 0);
      load_in    : in  std_logic;
      unload_in  : in  std_logic;
      start_in   : in  std_logic;
      inverse_in : in  std_logic;
      busy_out   : out std_logic);
  end component;

  -- component ports
  signal clk        : std_logic := '0';
  signal rst_n      : std_logic;
  signal data_in    : std_logic_vector(7 downto 0);
  signal data_out   : std_logic_vector(7 downto 0);
  signal key_in     : std_logic_vector(7 downto 0);
  signal load_in    : std_logic;
  signal unload_in  : std_logic;
  signal start_in   : std_logic;
  signal inverse_in : std_logic;
  signal busy_out   : std_logic;

  type testvec_t is array (0 to 15) of std_logic_vector(7 downto 0);
  type testvec_int_t is array (0 to 15) of integer;

  -- E[k](x) denotes encrypt x using key k
  --      
  -- let x_0 = {0}^128 and k_0 = {1}^128
  -- and 
  -- x_{i+1} = E[k_i](x_i)  (i > 0)
  -- k_{i+1} = x_i          (i > 0)
  -- then x_1000 should equeal to 'result'
  constant result : testvec_int_t :=
    (16#31#, 16#a5#, 16#05#, 16#a0#, 16#41#, 16#86#, 16#1e#, 16#ba#,
     16#da#, 16#85#, 16#4d#, 16#b9#, 16#40#, 16#f2#, 16#98#, 16#9f#);


  signal key, data : testvec_t;

begin  -- architecture test3

  DUT : aes
    port map (
      clk        => clk,
      rst_n      => rst_n,
      data_in    => data_in,
      data_out   => data_out,
      key_in     => key_in,
      load_in    => load_in,
      unload_in  => unload_in,
      start_in   => start_in,
      inverse_in => inverse_in,
      busy_out   => busy_out);

  -- clock generation
  clk <= not clk after 5 ns;            -- 100 MHz clock

  gen_reset : process
  begin
    rst_n <= '0';
    wait for 20 ns;
    rst_n <= '1';
    wait;
  end process gen_reset;


  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    data_in   <= (others => '0');
    key_in    <= (others => '0');
    load_in   <= '0';
    unload_in <= '0';

    inverse_in <= '0';
    start_in   <= '0';

    wait until rising_edge(clk) and rst_n = '1';

    for t in 0 to 1 loop
      wait until rising_edge(clk);
    end loop;  -- t

    ---------------------------------------------------------------------------
    -- load first input
    ---------------------------------------------------------------------------
    inverse_in <= '0';
    for i in 0 to 15 loop
      wait until falling_edge(clk);
      -- load data on falling edge (so that register hold&setup times are
      -- not violated)
      data_in <= (others => '0');
      key_in  <= (others => '1');
      key(i)  <= (others => '0');
      load_in <= '1';
    end loop;  -- i

    wait until falling_edge(clk);
    load_in  <= '0';
    start_in <= '1';

    wait until falling_edge(clk);
    start_in <= '0';


    -- compute
    wait until rising_edge(clk) and busy_out = '0';

    for t in 0 to 998 loop
      -- calculate aes 1000 times
      -- unload & load back the output

      for i in 0 to 15 loop
        wait until falling_edge(clk);
        unload_in <= '1';
        load_in   <= '1';
        data_in   <= data_out;
        key_in    <= key(i);
        key(i)    <= data_out;
      end loop;  -- i

      wait until falling_edge(clk);
      load_in   <= '0';
      unload_in <= '0';
      start_in  <= '1';
      wait until falling_edge(clk);
      start_in  <= '0';


      -- compute
      wait until rising_edge(clk) and busy_out = '0';
    end loop;

    for i in 0 to 15 loop
      wait until falling_edge(clk);
      unload_in <= '1';
      wait until rising_edge(clk);
      assert (data_out = std_logic_vector(to_unsigned(result(i), 8)))
        report "test failed" severity failure;
    end loop;  -- i

    report "tests done!" severity warning;
    wait;

  end process WaveGen_Proc;

end architecture test3;