mixcolumns.vhd

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

-------------------------------------------------------------------------------
-- Title      : A compact 8bit AES encryption core
-------------------------------------------------------------------------------
-- File       : mixcolumns.vhd
-- Author     : Timo Alho  <[e-mail]>
-- Date       : 27.2.2006
-------------------------------------------------------------------------------
-- Description: MixColumns entity
-------------------------------------------------------------------------------
-- Disclaimer: The AES encryption core provided here is distributed AS
-- IS without any warranty of any kind either expressed or implied,
-- including, without limitation, warranties of merchantability,
-- fitness for a particular purpose or non infringement of
-- intellectual property rights.
-------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity mixcolumns is
  port(
    clk        : in  std_logic;
    start_in   : in  std_logic;
    inverse_in : in  std_logic;         -- '1' = inverse transformation

    data_in    : in  std_logic_vector (7 downto 0);  -- input data
    data0_out  : out std_logic_vector (7 downto 0);  -- output data
    data1_out  : out std_logic_vector (7 downto 0);  -- output data
    data2_out  : out std_logic_vector (7 downto 0);  -- output data
    data3_out  : out std_logic_vector (7 downto 0)   -- output data
    );
end mixcolumns;