readme

VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits

************************************************************************
A compact 8bit AES encryption core

************************************************************************
Contact: Timo Alho <[e-mail]> 
Date: 27.2.2006

************************************************************************
Disclaimer: The AES encryption core provided here is distributed AS IS
without any warranty of any kind either expressed or implied,
including, without limitation, warranties of merchantability, fitness
for a particular purpose or non infringement of intellectual property
rights.

************************************************************************

This design is an Advanced Encryption Standard (AES) encryption core
implemented using VHDL language. The design and evaluation of the core
is presented in [1]. The core supports encryption with 128 bit
keys. Encrypting 128 bit block of data takes 160 clock cycles. The
design is fully synthesisable and requires no external components
(e.g. memories). Area consumption using compact S-box implementation
(not included, but [2] presents verilog sources for compact
implementation) is approximately 3100 gates.

Following files are needed to build the core (in hierarchical order,
top-level last):
- src/bytepermutation.vhd
- src/bytepermutation_fwd_rtl.vhd
- src/keyexpansion.vhd
- src/keyexpansion_fwd_rtl.vhd
- src/subbytes.vhd
- src/subbytes_lut.vhd
- src/mixcolumns.vhd
- src/mixcolumns_fwd_rtl.vhd
- src/par2ser.vhd
- src/aes.vhd

Three automatic testebenches can be found in src directory
- src/aes_tb.vhd	# testbench entity
- src/aes_tb_test1.vhd	# basic test
- src/aes_tb_test2.vhd	# test simultaneous loading and unloading
- src/aes_tb_test3.vhd	# extensive Monte Carlo test

REFERENCES 

[1] Panu H鋗鋖鋓nen, Timo Alho, Marko H鋘nik鋓nen, Timo D. H鋗鋖鋓nen,
"Design and Implementation of Low-area and Low-power AES Encryption
Hardware Core", 9th Euromicro Conference on Digital System Design -
Architectures, Methods and Tools (DSD 2006), Cavtat, Croatia, August
30, 2006 - September 1, 2006.

[2] David Canright, "A Very Compact Rijndael S-box", Naval
Postgraduate School Technical Report: NPS-MA-05-001, 2005, available
online http://web.nps.navy.mil/~dcanrig/pub/NPS-MA-05-001.pdf