📄 makefile
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COMP = vcomFLAGS = -work work -check_synthesis#rtl -level source codesRTL_SRC = \src/bytepermutation.vhd \src/bytepermutation_fwd_rtl.vhd \src/keyexpansion.vhd \src/keyexpansion_fwd_rtl.vhd \src/subbytes.vhd \src/subbytes_lut.vhd \src/mixcolumns.vhd \src/mixcolumns_fwd_rtl.vhd \src/par2ser.vhd \src/aes.vhd#testbech source codesTB_SRC = \src/aes_tb.vhd \src/aes_tb_test1.vhd \src/aes_tb_test2.vhd \src/aes_tb_test3.vhd.PHONY : core test1 test2 test3 compile#builds a single file from the design filescore : cat $(RTL_SRC) > aes_core.vhdtest1 : compile vsim -c -do "run 4000 ns" "work.aes_tb(test1)"test2 : compile vsim -c -do "run 30000 ns" "work.aes_tb(test2)"test3 : compile vsim -c -do "run 1700 us" "work.aes_tb(test3)"compile : $(COMP) $(FLAGS) $(RTL_SRC) $(COMP) $(FLAGS) $(TB_SRC)
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