control1.map.rpt

来自「16位CUPIP核,完全运行的好的东西,可以直接拿来用的!」· RPT 代码 · 共 201 行 · 第 1/5 页

+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+-----------------------------+--------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Apr 25 16:54:38 2006            ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1.21 SJ Full Version ;
; Revision Name               ; control1                                         ;
; Top-level Entity Name       ; control1                                         ;
; Family                      ; Cyclone                                          ;
; Total logic elements        ; 91                                               ;
; Total pins                  ; 46                                               ;
; Total virtual pins          ; 0                                                ;
; Total memory bits           ; 0                                                ;
; Total PLLs                  ; 0                                                ;
+-----------------------------+--------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Top-level entity name                                              ; control1     ; control1      ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;