38decoder.tan.rpt

使用Verilog硬件描述语言编程的38译码器

Timing Analyzer report for 38decoder
Wed Jun 06 17:28:49 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.898 ns   ; A    ; D0 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 13.898 ns       ; A    ; D0 ;
; N/A   ; None              ; 13.046 ns       ; B    ; D0 ;
; N/A   ; None              ; 12.959 ns       ; C    ; D0 ;
; N/A   ; None              ; 12.599 ns       ; A    ; D1 ;
; N/A   ; None              ; 12.596 ns       ; A    ; D6 ;
; N/A   ; None              ; 12.595 ns       ; A    ; D3 ;
; N/A   ; None              ; 12.588 ns       ; A    ; D7 ;
; N/A   ; None              ; 12.156 ns       ; A    ; D5 ;
; N/A   ; None              ; 12.155 ns       ; A    ; D2 ;
; N/A   ; None              ; 12.154 ns       ; A    ; D4 ;
; N/A   ; None              ; 11.746 ns       ; B    ; D3 ;
; N/A   ; None              ; 11.741 ns       ; B    ; D7 ;
; N/A   ; None              ; 11.739 ns       ; B    ; D6 ;
; N/A   ; None              ; 11.738 ns       ; B    ; D1 ;
; N/A   ; None              ; 11.660 ns       ; C    ; D1 ;
; N/A   ; None              ; 11.660 ns       ; C    ; D7 ;
; N/A   ; None              ; 11.657 ns       ; C    ; D3 ;
; N/A   ; None              ; 11.657 ns       ; C    ; D6 ;
; N/A   ; None              ; 11.309 ns       ; B    ; D2 ;
; N/A   ; None              ; 11.307 ns       ; B    ; D4 ;
; N/A   ; None              ; 11.306 ns       ; B    ; D5 ;
; N/A   ; None              ; 11.227 ns       ; C    ; D2 ;
; N/A   ; None              ; 11.226 ns       ; C    ; D4 ;
; N/A   ; None              ; 11.223 ns       ; C    ; D5 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 06 17:28:48 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38decoder -c 38decoder --timing_analysis_only
Info: Longest tpd from source pin "A" to destination pin "D0" is 13.898 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 8; PIN Node = 'A'
    Info: 2: + IC(6.886 ns) + CELL(0.590 ns) = 8.945 ns; Loc. = LC_X1_Y6_N4; Fanout = 1; COMB Node = '1'
    Info: 3: + IC(2.829 ns) + CELL(2.124 ns) = 13.898 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'D0'
    Info: Total cell delay = 4.183 ns ( 30.10 % )
    Info: Total interconnect delay = 9.715 ns ( 69.90 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Jun 06 17:28:49 2007
    Info: Elapsed time: 00:00:01