38decoder.map.summary

来自「使用Verilog硬件描述语言编程的38译码器」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Wed Jun 06 17:28:58 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : 38decoder
Top-level Entity Name : 38decoder
Family : Cyclone
Total logic elements : 8
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0