shijizhi.tan.qmsg

来自「十进制加法计数器.VHDL程序,可在Quratus 2中运行」· QMSG 代码 · 共 9 行 · 第 1/2 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin a\[1\] b\[1\] 6.541 ns register " "Info: tco from clock clkin to destination pin a\[1\] through register b\[1\] is 6.541 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.745 ns + Longest register " "Info: + Longest clock path from clock clkin to source register is 2.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.711 ns) 2.745 ns b\[1\] 2 REG LC_X2_Y13_N4 5 " "Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.276 ns" { clkin b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.42 % " "Info: Total cell delay = 2.180 ns ( 79.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns 20.58 % " "Info: Total interconnect delay = 0.565 ns ( 20.58 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.572 ns + Longest register pin " "Info: + Longest register to pin delay is 3.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[1\] 1 REG LC_X2_Y13_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(2.124 ns) 3.572 ns a\[1\] 2 PIN PIN_1 0 " "Info: 2: + IC(1.448 ns) + CELL(2.124 ns) = 3.572 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'a\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.572 ns" { b[1] a[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 59.46 % " "Info: Total cell delay = 2.124 ns ( 59.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.448 ns 40.54 % " "Info: Total interconnect delay = 1.448 ns ( 40.54 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.572 ns" { b[1] a[1] } "NODE_NAME" } } }  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.572 ns" { b[1] a[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clkin a\[3\] b\[3\] 6.374 ns register " "Info: Minimum tco from clock clkin to destination pin a\[3\] through register b\[3\] is 6.374 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.745 ns + Shortest register " "Info: + Shortest clock path from clock clkin to source register is 2.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.711 ns) 2.745 ns b\[3\] 2 REG LC_X2_Y13_N9 4 " "Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N9; Fanout = 4; REG Node = 'b\[3\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.276 ns" { clkin b[3] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.42 % " "Info: Total cell delay = 2.180 ns ( 79.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns 20.58 % " "Info: Total interconnect delay = 0.565 ns ( 20.58 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.405 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[3\] 1 REG LC_X2_Y13_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N9; Fanout = 4; REG Node = 'b\[3\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { b[3] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(2.108 ns) 3.405 ns a\[3\] 2 PIN PIN_142 0 " "Info: 2: + IC(1.297 ns) + CELL(2.108 ns) = 3.405 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'a\[3\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.405 ns" { b[3] a[3] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 61.91 % " "Info: Total cell delay = 2.108 ns ( 61.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.297 ns 38.09 % " "Info: Total interconnect delay = 1.297 ns ( 38.09 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.405 ns" { b[3] a[3] } "NODE_NAME" } } }  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[3] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "3.405 ns" { b[3] a[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 04 11:04:31 2007 " "Info: Processing ended: Sat Aug 04 11:04:31 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}