shijizhi.vhd

来自「十进制加法计数器.VHDL程序,可在Quratus 2中运行」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;

entity shijizhi is
 port
  (clkin:in std_logic;
     a:out integer range 0 to 9;
     c:out std_logic);
 end;
architecture liu of shijizhi is
begin
  process(clkin)
  variable b:integer range 0 to 9;
  variable d:std_logic;
  begin
    if rising_edge(clkin) then 
        if b=9 then 
           b:=0; 
           d:='1';       
        else b:=b+1;
             d:='0';
        end if;
    end if;
    a<=b;
    c<=d; 
  end process;
end;