shijizhi.tan.qmsg

来自「十进制加法计数器.VHDL程序,可在Quratus 2中运行」· QMSG 代码 · 共 9 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 04 11:04:30 2007 " "Info: Processing started: Sat Aug 04 11:04:30 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off shijizhi -c shijizhi --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shijizhi -c shijizhi --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node clkin is an undefined clock" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 6 -1 0 } } { "d:/quartus ii/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus ii/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register b\[1\] b\[2\] 275.03 MHz Internal " "Info: Clock clkin Internal fmax is restricted to 275.03 MHz between source register b\[1\] and destination register b\[2\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.178 ns + Longest register register " "Info: + Longest register to register delay is 2.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[1\] 1 REG LC_X2_Y13_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.292 ns) 0.845 ns add~8 2 COMB LC_X2_Y13_N6 1 " "Info: 2: + IC(0.553 ns) + CELL(0.292 ns) = 0.845 ns; Loc. = LC_X2_Y13_N6; Fanout = 1; COMB Node = 'add~8'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "0.845 ns" { b[1] add~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.867 ns) 2.178 ns b\[2\] 3 REG LC_X2_Y13_N2 5 " "Info: 3: + IC(0.466 ns) + CELL(0.867 ns) = 2.178 ns; Loc. = LC_X2_Y13_N2; Fanout = 5; REG Node = 'b\[2\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.333 ns" { add~8 b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.159 ns 53.21 % " "Info: Total cell delay = 1.159 ns ( 53.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.019 ns 46.79 % " "Info: Total interconnect delay = 1.019 ns ( 46.79 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.178 ns" { b[1] add~8 b[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.745 ns + Shortest register " "Info: + Shortest clock path from clock clkin to destination register is 2.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.711 ns) 2.745 ns b\[2\] 2 REG LC_X2_Y13_N2 5 " "Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N2; Fanout = 5; REG Node = 'b\[2\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.276 ns" { clkin b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.42 % " "Info: Total cell delay = 2.180 ns ( 79.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns 20.58 % " "Info: Total interconnect delay = 0.565 ns ( 20.58 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.745 ns - Longest register " "Info: - Longest clock path from clock clkin to source register is 2.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.711 ns) 2.745 ns b\[1\] 2 REG LC_X2_Y13_N4 5 " "Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.276 ns" { clkin b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.42 % " "Info: Total cell delay = 2.180 ns ( 79.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns 20.58 % " "Info: Total interconnect delay = 0.565 ns ( 20.58 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[1] } "NODE_NAME" } } }  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.178 ns" { b[1] add~8 b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "2.745 ns" { clkin b[1] } "NODE_NAME" } } }  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0}