shijizhi.fit.rpt

十进制加法计数器.VHDL程序,可在Quratus 2中运行

; M4K buffers                ; 0 / 468 ( 0 % )      ;
; R4s                        ; 2 / 7,520 ( < 1 % )  ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 6.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 1                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 6.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Sat Aug 04 11:04:22 2007
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off shijizhi -c shijizhi
Info: Selected device EP1C3T144C8 for design shijizhi
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 6 pins of 6 total pins
    Info: Pin a[3] not assigned to an exact location on the device
    Info: Pin a[2] not assigned to an exact location on the device
    Info: Pin a[1] not assigned to an exact location on the device
    Info: Pin a[0] not assigned to an exact location on the device
    Info: Pin c not assigned to an exact location on the device
    Info: Pin clkin not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal clkin to use Global clock in PIN 17
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 5 (unused VREF, 3.30 VCCIO, 0 input, 5 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Info: Details of I/O bank after I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  13 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 1.871 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'b[1]'
    Info: 2: + IC(0.065 ns) + CELL(0.590 ns) = 0.655 ns; Loc. = LAB_X2_Y13; Fanout = 1; COMB Node = 'add~8'
    Info: 3: + IC(0.349 ns) + CELL(0.867 ns) = 1.871 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'b[2]'
    Info: Total cell delay = 1.457 ns ( 77.87 % )
    Info: Total interconnect delay = 0.414 ns ( 22.13 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Aug 04 11:04:27 2007
    Info: Elapsed time: 00:00:04